文件名称：基于双比特算法的新型除法器
文件大小：127KB
文件格式：PDF
更新时间：2017-08-26 09:14:16
双比特算法 fpga 复数除法器
A n ov el d iv ider bas ed on dual 2b it alg or ithm and it s V LSI im plemen tati on are pres en ted. C om pared w ith the d iv ider o f MI PS m icr opr ocess or ,it decreas es the av erag e ex ecu ting cy cles by 5215 % wh ile it s max imum delay i s alm os t the s ame and it s tran 2 s i s t or c oun t increas es by 60 %. Fur therm ore ,the s imu lati on resu lt ind icates that the power c onsum pti on decreas es t o 1113 % w ith the s ame pr ocess ing ab ility.