文件名称:CAN verilog
文件大小:33KB
文件格式:GZ
更新时间:2014-12-21 15:12:44
can VERILOG
在FPGA中用verilog hdl实现CAN控制器,具体实现见代码
【文件预览】:
can_register_asyn_syn.v
can_crc.v
can_top.v
can_fifo.v
can_register_asyn.v
can_registers.v
can_bsp.v
can_acf.v
can_register.v
can_defines.v
can_register_syn.v
README.txt
can_ibo.v
can_btl.v