文件名称：intel-xeon-scalable-processor-throughput-latency.pdf
文件大小：2.54MB
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更新时间：2023-08-04 05:00:15
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The table describes throughput and latency for processors with two FMA units, assuming all sources come from the FMA unit. See FMA latency chapter in the optimization guide for more information. Memory latencies are assuming Data Cache Unit (DCU) hit