文件名称：ARM7源码-Verilog
文件大小：61KB
文件格式：RAR
更新时间：2013-06-24 14:42:35
ARM7 Verilog ALU ASM MLA
The goal of the project was to design and synthesize an ARM7 microprocessor with a unified cache and IEEE754 compliant floating-point unit within a ten-week time frame. The design was broken up and given to several project groups
【文件预览】：
arm7
----SuperCPSR.v(4KB)
----testbench_barrel.v(4KB)
----test_barrel.out(6KB)
----testbench_booth.v(5KB)
----and10.regout(121B)
----and10.dmemr(162B)
----and10.dmem(171B)
----addr_reg.v(775B)
----CPUside.v(26KB)
----test_alu.out(4KB)
----barrel.v(4KB)
----arm7.dmem(57B)
----arm7.dmemout(54B)
----wd_reg.v(573B)
----testbench_AVLMemory.v(4KB)
----arm7.regsr(55B)
----armdatapath.v(9KB)
----and10.imem(513B)
----regfile.v(20KB)
----armcontroller.v(42KB)
----testbench_regfile.v(4KB)
----Memoryside.v(7KB)
----MemoryInterface.v(2KB)
----and10.dmemout(162B)
----SimpleMemory.v(4KB)
----shift_maker.v(1KB)
----testbench_dedsec.v(10KB)
----testbench_regfile3.v(4KB)
----testbench_regfile4.v(4KB)
----test_addr_reg.out(650B)
----arm7.imem(228B)
----testbench_regfile2.v(4KB)
----test_reg.out(1KB)
----do_verilog(266B)
----test_wd_reg.out(828B)
----arm7_sys.v(2KB)
----arm7.dmemr(54B)
----AVLMemory.v(5KB)
----testbench_arm7.v(10KB)
----alu_structural.v(15KB)
----testbench_wd_reg.v(2KB)
----test_regfile.out(7KB)
----alu.v(5KB)
----test_booth.out(616B)
----sign_extend.v(4KB)
----booth.v(2KB)
----testbench_SimpleMemory.v(4KB)
----testbench_CPUside.v(7KB)
----and10.regsr(121B)
----clock.v(304B)
----arm7.regout(55B)
----testbench_controller.v(9KB)
----testbench_memory.v(3KB)
----exception.mem(190B)
----defines.v(4KB)
----accessories.v(6KB)
----testbench_alu.v(5KB)
----arm7.v(3KB)
----testbench_addr_reg.v(2KB)