文件名称：飞思卡尔的DDR3 pcb布局布线要求
文件大小：514KB
文件格式：PDF
更新时间：2018-06-15 04:06:03
ddr3 layout designe
The design guidelines presented in this application note apply to products that leverage the DDR3 SDRAM IP core, and they are based on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer