文件名称：七段译码器的设计实验
文件大小：301KB
文件格式：RAR
更新时间：2015-04-21 13:42:47
七段译码器、verilog语言
用verilog语言写的七段译码器的实验，尽管代码挺简洁的，但用处很大，对学习数字逻辑电路的同学很有帮助。
【文件预览】：
lab03_bcd7seg
----Vr7seg.qsf(5KB)
----Verilog2.v(618B)
----Vr7seg.vwf(19KB)
----db()
--------Vr7seg.cmp.cdb(7KB)
--------Vr7seg.simfam(10B)
--------Vr7seg.map.ecobp(28B)
--------Vr7seg.rtlv_sg.cdb(2KB)
--------Vr7seg.cmp_merge.kpt(343B)
--------Vr7seg.cmp.logdb(4B)
--------Vr7seg.fnsim.qmsg(3KB)
--------Vr7seg.eco.cdb(175B)
--------Vr7seg.(1).cnf.hdb(761B)
--------Vr7seg.cbx.xml(88B)
--------Vr7seg.cmp0.ddb(67KB)
--------Vr7seg.rtlv.hdb(9KB)
--------Vr7seg.asm_labs.ddb(25KB)
--------Vr7seg.asm.qmsg(2KB)
--------Vr7seg.fit.qmsg(20KB)
--------Vr7seg.sgdiff.hdb(9KB)
--------Vr7seg.map_bb.cdb(803B)
--------Vr7seg.cmp.kpt(337B)
--------wed.wsf(11KB)
--------Vr7seg.map.bpm(729B)
--------Vr7seg.fnsim.cdb(2KB)
--------Vr7seg.(1).cnf.cdb(1KB)
--------prev_cmp_Vr7seg.qmsg(3KB)
--------Vr7seg.pre_map.hdb(9KB)
--------Vr7seg.map.qmsg(4KB)
--------Vr7seg.cmp.bpm(744B)
--------Vr7seg.db_info(151B)
--------Vr7seg.cmp.hdb(8KB)
--------Vr7seg.sld_design_entry_dsc.sci(168B)
--------Vr7seg.map_bb.logdb(4B)
--------Vr7seg.rtlv_sg_swap.cdb(659B)
--------Vr7seg.map_bb.hdb(7KB)
--------Vr7seg.(0).cnf.hdb(1KB)
--------Vr7seg.sim.rdb(4KB)
--------Vr7seg.lpc.rdb(454B)
--------Vr7seg.map.cdb(2KB)
--------Vr7seg.cmp.ecobp(28B)
--------Vr7seg.lpc.html(2KB)
--------Vr7seg.sld_design_entry.sci(168B)
--------Vr7seg.cmp.tdb(5KB)
--------Vr7seg.map.kpt(337B)
--------prev_cmp_Vr7seg.sim.qmsg(3KB)
--------Vr7seg.sim.cvwf(1KB)
--------Vr7seg.sgdiff.cdb(1KB)
--------Vr7seg.map.hdb(8KB)
--------Vr7seg.(0).cnf.cdb(1KB)
--------Vr7seg.lpc.txt(2KB)
--------Vr7seg.hier_info(3KB)
--------Vr7seg.syn_hier_info(0B)
--------Vr7seg.cmp.rdb(24KB)
--------Vr7seg.map.logdb(4B)
--------Vr7seg.tan.qmsg(5KB)
--------prev_cmp_Vr7seg.map.qmsg(4KB)
--------Vr7seg.tmw_info(304B)
--------Vr7seg.pre_map.cdb(2KB)
--------Vr7seg.sim.qmsg(3KB)
--------Vr7seg.hif(1KB)
--------Vr7seg.eds_overflow(2B)
--------Vr7seg.fnsim.hdb(9KB)
--------Vr7seg.sim.hdb(3KB)
--------Vr7seg.tis_db_list.ddb(188B)
----debug()
--------Vr7seg.sim.rpt(28KB)
--------Vr7seg.pin(101KB)
--------Vr7seg.flow.rpt(8KB)
--------Vr7seg.pof(2MB)
--------Vr7seg.tan.summary(719B)
--------Vr7seg.asm.rpt(7KB)
--------Vr7seg.map.rpt(17KB)
--------Vr7seg.fit.rpt(225KB)
--------Vr7seg.sof(1.69MB)
--------Vr7seg.done(26B)
--------Vr7seg.tan.rpt(16KB)
--------Vr7seg.map.summary(456B)
--------Vr7seg.fit.summary(603B)
----incremental_db()
--------compiled_partitions()
--------README(653B)
----Vr7seg.qws(934B)
----Vr7seg.v(758B)
----Vr7seg.qpf(1KB)
----Vr7seg.dpf(239B)