文件名称：DSP设计流程指南(PDF).pdf
文件大小：453KB
文件格式：PDF
更新时间：2012-10-31 13:13:59
DSP设计流程指南
This user guide introduces the DSP Builder Advanced Blockset, including the key differences between the DSP Builder standard and advanced blocksets with advice about when to use each blockset. It also provides information about interoperability between the blocksets and with other tools. The Advanced Blockset The DSP Builder Advanced Blockset consists of a number of Simulink libraries that allow you to implement DSP designs quickly and easily. The blockset is based on a high level synthesis technology that optimizes the high level, untimed netlist into low level, pipelined hardware targeted to your chosen FPGA device and chosen clock rate. The hardware is written out as plain text VHDL, along with scripts that integrate with the Quartus II software and the ModelSim simulator. The combinations of these features allows you to create a design without needing intimate device knowledge, and then generate a high quality implementation that runs on a variety of FPGA families with different hardware architectures. By specifying your desired clock frequency you can solve timing closure issues by generating RTL that is pipelined to meet your goal. Filters within the blockset automatically use a high clock rate to increase folding, and reduce hardware size. Example designs are provided as a starting point and to illustrate the design possibilities.