文件名称：IMGMIPSFPGA资料.pdf
文件大小：368KB
文件格式：PDF
更新时间：2022-08-12 09:41:00
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MIPSfpga provides the RTL source code of the MIPS microAptiv UP core for implementation on an FPGA, together with teaching materials. The MIPS microAptiv UP core is a member of the same microcontroller family found in many embedded devices, including the popular PIC32MZ microcontroller from Microchip and Samsung’s new Artik1. The teaching materials will show you how to use this core as part of a Computer Architecture course, paving the way for your students to explore how a commercial pipelined processor core works inside and to use this core in their projects, in effect creating their own SoC designs. With its long heritage and excellent documentation, MIPS is the preferred choice of RISC architecture for many teachers around the world. But in the past, to demonstrate key concepts, teachers had to settle for creating partial ‘MIPS-like’ cores or using unofficial copies of dubious heritage. Not now! MIPSfpga is the real ‘industrial’ RTL, non-obfuscated, and available freely for academic use.