Quartus宏模块的应用lpm_ram_dp（双端口ram）
Altera官网提供的时序图：
Altera官网提供的模块：
仿真程序：
lpm_ram_dp_testbench
1 `timescale 1ns/1ns
2 `define clk_cycle 5
3 module testbench;
4 reg [15:0]data;
5 reg [6:0]wraddress;
6 reg wren;
7 reg [6:0]rdaddress;
8 reg rden;
9 reg wrclock;
10 reg rdclock;
11
12 reg clk_sys;
13 wire [15:0]q;
14 always #`clk_cycle clk_sys=~clk_sys;
15
16 initial
17 begin
18 data=0;
19 wraddress=0;
20 wren=0;
21 rdaddress=0;
22 rden=0;
23 wrclock=0;
24 rdclock=0;
25 clk_sys=0;
26 end
27
28 always @(posedge clk_sys)
29 begin
30 wrclock<=~wrclock;
31 end
32
33 always @(negedge clk_sys)
34 begin
35 if(wrclock==0)
36 begin
37 if(wraddress==10)
38 begin
39 wren<=0;
40 rden<=1;
41 end
42 else
43 begin
44 wren<=1;
45 rden<=0;
46 wraddress<=wraddress+1;
47 data<=data+1;
48 end
49 end
50 else
51 begin
52 wraddress<=wraddress;
53 data<=data;
54 end
55 end
56
57 always @(posedge clk_sys)
58 begin
59 rdclock<=~rdclock;
60 end
61
62 always @(negedge rdclock)
63 begin
64 if(rden==1)
65 begin
66 if(rdaddress==10)
67 begin
68 rden=0;
69 end
70 else
71 rdaddress<=rdaddress+1;
72 end
73 end
74 DspBus m0(.wren(wren),.rden(rden),.wrclock(wrclock),
75 .rdclock(rdclock),.data(data),.rdaddress(rdaddress),
76 .wraddress(wraddress),.q(q));
77
78 endmodule
