VHDL奇怪的语句错误（语法）

We've been having a really strange, yet simple when-statement error in our VHDL code, by now we've tried everything we could think of but the program still complains about a syntax error (near the first "when") in the statement.

我们的VHDL代码中有一个非常奇怪但简单的if语句错误,现在我们已经尝试了我们能想到的一切,但程序仍然抱怨语法错误(接近第一个“何时”)声明。

    ALUsource <= '0';
            with FuncCode select
                    ALUcontrol <=   "10" when "0x20",
                                    "10" when "0x22",
                                    "00" when "0x24",
                                    "01" when "0x25",
                                    "11" when "0x2A",
                                    "00" when others;

            with FuncCode select
                    SubFlag <=     '1' when "0x22",
                                   '0' when others;

            with FuncCode select   
                    W_ena <=       '1' when "0x20",
                                   '1' when "0x22",
                                   '1' when "0x24",
                                   '1' when "0x25",
                                   '1' when "0x2A",
                                   '0' when others;


    when OPcode /= "000000"
            with OPcode select
                    ALUcontrol <=   "10" when "0x08",
                                    "11" when "0x0A",
                                    "00" when others;

1 个解决方案

#1

As previous comments said, this example is not complete and therefore hard to tell where the error is, but i take a guess and suggest writing

正如之前的评论所说,这个例子并不完整,因此很难说出错误在哪里,但我猜测并建议写作

when OPcode /= "000000" =>

当OPcode / =“000000”=>时

instead of

when OPcode /= "000000"

当OPcode / =“000000”时

#1