ncsim仿真VHDL
1、文件列表
ctrl.vhd
design_io.vhd
tb.vhd
compile.nc
simulate.nc
./shm/shmtb.tcl
2、 Compile你的VHDL设计文件[compile.nc]
#!/bin/csh -f
#---------------------------------------------------------------------- # ------------------------------------------------------------------- #
# Directories location
# ------------------------------------------------------------------- # setenv src_dir ../src
setenv tb_dir ./
setenv work_dir ./lib # ------------------------------------------------------------------- #
# Library creation
# ------------------------------------------------------------------- # setenv CDS_VHDL /user/EDA_Tools/Cadence/IUS_11.10_lnx86/tools.lnx86/inca echo "softinclude $CDS_VHDL/files/cds.lib" > cds.lib
echo "define work ./lib" >> cds.lib
echo " " > hdl.var
mkdir -p $work_dir # Compile Key Expander
#
ncvhdl -v93 -work work $src_dir/ctrl.vhd #
# Compile Testbench
#
ncvhdl -v93 -work work $tb_dir/design_io.vhd
ncvhdl -v93 -work work $tb_dir/tb.vhd
compile.nc
3、simulate生成波形[simulate.nc]
#!/bin/csh -f
#----------------------------------------------------------------------
# ------------------------------------------------------------------- #
# Elaborating the Design
# ------------------------------------------------------------------- # ncelab -work work work.tb:beh -access wrc # ******************************************************************* #
# ------------------------------------------------------------------- #
# Simulating the Design
# ------------------------------------------------------------------- # ncsim tb +acssce+rwc -MESSAGES -input ./shm/shmtb.tcl
simulate.nc
4、Tcl脚本文件控制生成波形[./shm/shmtb.tcl]
#生成VCD文件
database -open ./waves/tbvcdwaves -vcd -default
probe -create beh -depth all -all -vcd -database ./waves/tbvcdwaves #生成shm文件
database -open ./waves/tbwaves -shm -default
probe -create beh -depth all -all -shm -database ./waves/tbwaves
run
exit
shmtb.tcl
5、 运行脚本run[run]
注意将相关文件权限更新为可执行
./compile.nc
./simulate.nc
run
6、使用simvison查看波形
simvision ./waves/tbwaves.shm/tbwaves.trn &