在VHDL中从数组中选择元素

I have an component that receives an array:

我有一个接收数组的组件：

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
use work.index_pkg.all;

entity update_reg is
    port (
    index         : in integer;
    number_data   : in array_integer(9 downto 0);
    output_number : out integer;
);
end update_reg;

architecture behavior of update_reg is
begin
process1 : process(index, number_data)
begin
    output_number <= number_data(index);
end process;    
end architecture;

The purpose is to have at the component's output the array's element specified by the index. I built the following tb to test its behaviour:

目的是在组件的输出处获得由索引指定的数组元素。我构建了以下tb来测试它的行为：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.index_pkg.all;


entity tb_update_reg is
end tb_update_reg;

architecture rtl of tb_update_reg is

component update_reg is
    port (
    index         : in integer;
    number_data   : in array_integer(9 downto 0);
    output_number : out integer
);
end component;

signal tb_index         : integer;
signal tb_number_data   : array_integer(9 downto 0);
signal tb_output_number : integer; 
begin
fill_process : process(tb_number_data)
begin
    for n in 0 to 9 loop
        tb_number_data(n) <= 10 - n;
    end loop;
end process;
stim_process : process
begin
    tb_index <= 6;
    wait for 2.0 ns;
    tb_index <= 0;
    wait for 2.0 ns;
    tb_index <= 9;
    wait for 2.0 ns;
    tb_index <= 4;
    wait for 2.0 ns;
    tb_index <= 1;
    wait for 2.0 ns;
end process;
upd_reg : update_reg
port map(
    index         => tb_index,
    number_data   => tb_number_data,
    output_number => tb_output_number
);
end architecture;

And I added a package where I included the declaration for the array integer:

我添加了一个包，其中包含了数组整数的声明：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


package index_pkg is     
type array_integer is array (natural range <>) of integer;
end;

I would expect the numbers 4/10/1/6/9. Instead, the simulation is frozen. Is there some aspect I am missing?

我期待数字4/10/1/6/9。相反，模拟被冻结。我缺少一些方面吗？

I would be grateful if anyone could help.

如果有人能提供帮助，我将不胜感激。

1 个解决方案

#1

You have two issues:

你有两个问题：

i) You need to initialise the signal tb_index to 6:

i）您需要将信号tb_index初始化为6：

signal tb_index         : integer := 6;

In VHDL all processes are executed at time 0 right at the start of the simulation. Without such initialisation, this line in your design:

在VHDL中，所有过程在模拟开始时的时间0执行。没有这样的初始化，你的设计中的这一行：

output_number <= number_data(index);

gets executed before the index signal has been given a value by this line:

在索引信号被此行赋值之前执行：

tb_index <= 6;

So, on the first delta cycle the value of index is the default for an integer, the leftmost value (-2^31-1), which of course is out of range.

因此，在第一个delta周期中，index的值是整数的默认值，最左边的值（-2 ^ 31-1），当然超出范围。

ii) You need a wait statement at the bottom of the stim_process process:

ii）您需要在stim_process进程底部的等待语句：

    wait for 2.0 ns;
    wait;
end process;

In VHDL all processes loop continuously. So, the stim_process process loops back to the top and so your simulation runs forever. wait; in VHDL means wait forever, which is what you need here.

在VHDL中，所有进程都在不断循环。因此，stim_process进程循环回到顶部，因此您的模拟将永远运行。等待;在VHDL中意味着永远等待，这就是你需要的。

Also, this line in your design has an extra semicolon:

此外，您的设计中的这一行还有一个额外的分号：

output_number : out integer;

it should be:

它应该是：

output_number : out integer

http://www.edaplayground.com/x/3JaN

#1