在verilog中如何使用“for循环”的变量'i'

An error comes out that Ki & Bi is not declared; I want to use the loop variable in changing the array cell I'm filling:

Ki&Bi未被宣布出现错误;我想在更改我填充的数组单元时使用循环变量:

module subbytes (C0,C1,C2,C3,A0,A1,A2,A3);

 input  [0:31] A0;
 input  [0:31] A1;
 input  [0:31] A2;
 input  [0:31] A3;
 wire [0:31] A0;
 wire [0:31] A1;
 wire [0:31] A2;
 wire [0:31] A3;

 output  [0:31] C0;
 output  [0:31] C1;
 output  [0:31] C2;
 output  [0:31] C3;
 reg   [0:31] C0;
 reg  [0:31] C1; 
 reg  [0:31] C2;
 reg  [0:31] C3;

 wire [0:7] K0 [0:3];
 wire [0:7] K1 [0:3]; 
 wire [0:7] K2 [0:3];
 wire [0:7] K3 [0:3];

 assign K0[0] = A0[0:7];
 assign K0[1] = A0[8:15];
 assign K0[2] = A0[16:23];
 assign K0[3] = A0[24:31];

 assign K1[0]=A1[0:7];
 assign K1[1]=A1[8:15];
 assign K1[2]=A1[16:23];
 assign K1[3]=A1[24:31];

 assign K2[0]=A2[0:7];
 assign K2[1]=A2[8:15];
 assign K2[2]=A2[16:23];
 assign K2[3]=A2[24:31];

 assign K3[0]=A3[0:7];
 assign K3[1]=A3[8:15];
 assign K3[2]=A3[16:23];
 assign K3[3]=A3[24:31];

 reg [2:0] i;
 reg [2:0] j;

 reg [0:7] B0 [0:3];
 reg [0:7] B1 [0:3];
 reg [0:7] B2 [0:3];
 reg [0:7] B3 [0:3];

 always @(*)
 begin
  for ( i = 0; i < 4; i = i + 1 )
  begin
   for ( j = 0; j < 4; j = j + 1 )
   begin

    // Here is the problem 'Ki is not declared ' as

    case(Ki[j])
       0: Bi[j]=8'h63;
       1: Bi[j]=8'h7c;
       2: Bi[j]=8'h77;
       3: Bi[j]=8'h7b;
    /* ... other assignments to Bi[j] ... */
     252: Bi[j]=8'hb0;
     253: Bi[j]=8'h54;
     254: Bi[j]=8'hbb;
     255: Bi[j]=8'h16;
    endcase
   end
  end

  assign C0={B0[0],B1[0],B2[0],B3[0]};
  assign C1={B1[1],B2[1],B3[1],B0[1]};
  assign C2={B2[2],B3[2],B0[2],B1[2]};
  assign C3={B3[3],B0[3],B1[3],B2[3]};

 end

endmodule

1 个解决方案

#1

Ki and Bi are never declared. Perhaps the SO is thinking the i in Ki corespondents to the reg [2:0] i;, which is false. I believe the SO want to reuse the case statement. If this is the case there are some options:

Ki和Bi从未被宣布过。也许SO正在考虑我对于reg [2:0] i的Ki回应者,这是错误的。我相信SO想要重用case语句。如果是这种情况,有一些选择:

Move the case statement into its own sub module and instantiate appropriately.

将case语句移动到自己的子模块中并进行适当的实例化。

Move the case statement into a function and call appropriately.

将case语句移动到函数中并适当调用。

Merge K1,...K3 into K with a large enough range and index appropriately. Same For B.

将K1,... K3合并到K中,并且具有足够大的范围和索引。相同的B.

Switch to SystemVerilog where double unpacked arrays are allowed. Example, K can be defined as logic [7:0] K [4][4];

切换到允许双重解包数组的SystemVerilog。例如,K可以定义为逻辑[7:0] K [4] [4];

#1