在for循环中使用变量来指定verilog中数组的索引

I am a newbie in verilog. As variables can not be assigned to index of an array, how I can code this one in verilog, so no compilation error will occur?

我是verilog的新手。由于变量不能分配给数组的索引，我如何在verilog中对此进行编码，因此不会出现编译错误？

module strMatch();

reg [15:0]str;
integer i;

reg [10*8-1:0]searchBuffer;

initial
begin
str = "ab";
searchBuffer = "qwertabjkl";

for (i=10;i>=2;i++)
    begin
   if(searchBuffer[(8*i-1:8*(i-2)]==str[15:0])
       begin
           $display("i");
       end
    end // end of for
end // end of initial

endmodule

1 个解决方案

#1

Firstly you have an extra bracket in your if statement which is causing a syntax error. However even after fixing that your code is still incorrect since you're using i on both sides of your bit selection.

首先，if语句中有一个额外的括号，导致语法错误。但是，即使在确定您的代码仍然不正确之后，因为您在位选择的两侧都使用了i。

If you're taking a slice, one of the indices has to be constant. Verilog has a special notation for taking a constant range:

如果你正在切片，其中一个指数必须是常数。 Verilog有一个特殊的符号表示：

if (searchBuffer[8*i+:16]==str[15:0])

This will use 8*i as the base and take a slice of 16 bits. Working example on EDA Playground.

这将使用8 * i作为基数并采用16位片。 EDA Playground上的工作示例。

Note there is also a - bit select:

注意还有一个位选择：

  reg [15:0] big_vect; 
  reg [0:15] little_vect; 

  big_vect[lsb_base_expr    +: width_expr] 
  little_vect[msb_base_expr +: width_expr] 

  big_vect[msb_base_expr    -: width_expr] 
  little_vect[lsb_base_expr -: width_expr]

#1