Synopsys ICC学习（2）.&ICC基本流程
1 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 # Suppress known and/or annoying messages
3 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 suppress_message {PSYN-040 PSYN-088 PSYN-058 PSYN-039 PSYN-024 RCEX-060 PSYN-087 PSYN-850 TFCHK-055}
5
6 # Suppress warnings about metal layer pitch that occurs during create_mw_lib:
7 suppress_message {TFCHK-049 TFCHK-050}
8
9 # Suppress warning that "43 logical cells do not have P/G pins" from check_mv_design -power_nets:
10 suppress_message {MV-597}
11
12 # Suppress warning about ignored DEF syntax and "Information" about "preferred wire track direction
13 # not being set" during read_def:
14 suppress_message {DDEFR-054 MWDEFR-159}
15
16 # Suppress warning about "skipping AHFS on don't touch high-fanout nets" during place_opt:
17 suppress_message {PSYN-1002}
18
19 # Suppress warnings about "Ignore pin on layer 0", "Ignore top cell pins with no ports",
20 # and "METAL pitch too small" during route_zrt_global -congestion_map_only true:
21 suppress_message {ZRT-026 ZRT-027 ZRT-030}
22
23 # Suppress warning about "P/G ports being on non-routing layer "UNKNOWN" " and warning about
24 # using Elmore instead of "clock_arnoldi" delay calculation model during clock_opt:
25 suppress_message {MWLIBP-311 CTS-352}
26
27 # Suppress warning about "not enough nets being routed" during route_opt:
28 suppress_message {RCEX-047}
29
30 # Suppress warning: Power connection/checking is skipped for 2666 power pins because the required power pin information cannot be found in logical libraries.
31 suppress_message {MV-510}
32
33 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
34 # Load useful "functions" or procedures, like "view"
35 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
36 source ../ref/tools/
37
38 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
39 # General useful settings
40 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
41 # Disable more-like page mode
42 set_app_var enable_page_mode false
43 # Don't want to see CMD-041 when creating new variables
44 set_app_var sh_new_variable_message false
45 # Increase history buffer from 20 commands to 100
46 history keep 100
47
48
49 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
50 # Enable logging of commands and everything by date/shell
51 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
52 set timestamp [clock format [clock scan now] -format "%Y-%m-%d_%H-%M"]
53 set sh_output_log_file "${synopsys_program_name}.log.[pid].$timestamp"
54 set sh_command_log_file "${synopsys_program_name}.cmd.[pid].$timestamp"
55
56
57 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
58 # Aliases
59 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
60 alias v view
61 alias rt "report_timing -nosplit"
62 alias rtm "report_timing -nosplit -delay min"
63 alias rc "report_constraint -all_violators -nosplit"
64 alias rq report_qor
65 alias h history
66 alias _ measure_time
67
68
69 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
70 # Logic Library settings
71 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
72 lappend search_path ../ref/db ../ref/tlup
73 set_app_var target_library "sc_max.db"
74 set_app_var link_library "* sc_max.db io_max.db ram16x128_max.db"
75 set_min_library sc_max.db -min_version sc_min.db
76 set_min_library io_max.db -min_version io_min.db
77 set_min_library ram16x128_max.db -min_version ram16x128_min.db
78
79
80 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 # RISC_CHIP setup variables
82 # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 set my_mw_lib risc_chip.mw
84 set mw_path "../ref/mw_lib"
85 set tech_file " ../ref/tech/cb13_6m.tf"
86 set tlup_map "../ref/tlup/cb13_6m.map"
87 set tlup_max "../ref/tlup/cb13_6m_max.tluplus"
88 set tlup_min "../ref/tlup/cb13_6m_min.tluplus"
89 set top_design "RISC_CHIP"
90 set verilog_file "./design_data/RISC_CHIP.v"
91 set sdc_file "./design_data/RISC_CHIP.sdc"
92 set def_file "./design_data/RISC_CHIP.def"
93 set ctrl_file "./scripts/opt_ctrl.tcl"
94 set derive_pg_file "./scripts/derive_pg.tcl"