FPGA ——Verilog语法示例-条件判断

generate begin
	if(DEBUG =="ON")begin
		ila  ila_u
		(
			.clk(clk),
			.probe0
			(
				{
					A1,
					A2,
					A3,
					A4
				}
			)
		);
	end
end
endgenerate