展讯平台gpio配置

时间：2024-03-17 07:33:34

gpio寄存器的说明

 

示例参考最后

 

3.6 Control Register

3.6.1 IO_MUX_CENTRAL_PIN_RF Register Address Map

Base address: 0x402A0000

Base address(Set Reg): 0x402A1000

Base address(Clear Reg): 0x402A2000

 

主要分为PIN_CTRLX，主要是片内外设的一些控制器的控制

 

以GPIO32为例

 

1 模式的选择

GPIO32对IO_MUX_CENTRAL_PIN_RF（地址为0x402A0000）的偏移

0x01EC

GPIO32

GPIO32

展讯平台gpio配置

 

一个引脚往往可以复用

展讯的每个引脚复用情况一般在SL8521E_GPIO_Spec_V1.0.xlsx表格里说明

24

B13

GPIO32

VIO1V8

1.8V,4.7K/20K

50K

PWMA

O

DBG_BUS13(G0)

O

GPIO32

I/O/T

比如GPIO32就可以作为好几个功能引脚

Function1 为空

Function2 PWMA

Function3 DBG_BUS13(G0)

Function4 GPIO32

这里Function的选择，就是通过GPIO32_fun_sel来选择的，比如设置为3的话，那么GPIO32引脚就设置成了GPIO模式，设置为1的话，就设置成了PWMA模式

 

2 gpio的控制

6.27.1 Overview

The GPIO module provides general purpose input and output signals. many of the GPIO pins are

multiplexed with other functions and system design trade-off must be exercised on selecting them.

All the GPIO pins can be programmed to be either input or output. When in input mode, they can

be programmed to trigger interrupt to the MCU.

 

#define GPIO_GROUP_NR (16)

int sprd_gpio_write(struct gpio_chip *chip, uint32_t offset,

uint32_t reg, int value)

{

struct sprd_gpio_chip *sprd_gpio = to_sprd_gpio(chip);

int group = offset / GPIO_GROUP_NR;

int bitof = offset & (GPIO_GROUP_NR - 1);

unsigned long addr = sprd_gpio->base_addr +

sprd_gpio->group_offset * group + reg;

int ret;

 

if (value)

ret = sprd_gpio->set_bits(chip, 1 << bitof, addr);

else

ret = sprd_gpio->clr_bits(chip, 1 << bitof, addr);

 

return ret;

}

 

gpio的值 方向 输出的值是由一组寄存器控制的，每16个GPIO为一组，每个组的偏移值为0x80

比如 GPIO0-GPIO15 为第一组，偏移值为0，寄存器基地址为0x40280000

GPIO16-GPIO31为第二组，偏移值为0x80，寄存器基地址为0x40280080

GPIO32-GPIO47为第三组，偏移值为0x100，寄存器基地址为0x40280100

GPIO48-GPIO63为第三组，偏移值为0x180，寄存器基地址为0x40280180

GPIO64-GPIO79为第三组，偏移值为0x200，寄存器基地址为0x40280200

GPIO80-GPIO95为第三组，偏移值为0x280，寄存器基地址为0x40280280

GPIO96-GPIO111为第三组，偏移值为0x300，寄存器基地址为0x40280300

GPIO112-GPIO127为第三组，偏移值为0x380，寄存器基地址为0x40280380

GPIO128-GPIO143为第三组，偏移值为0x400，寄存器基地址为0x40280400

GPIO144-GPIO159为第三组，偏移值为0x480，寄存器基地址为0x40280480

GPIO160-GPIO175为第三组，偏移值为0x500，寄存器基地址为0x40280500

依次类推

 

每组寄存器的功能如下宏和表格所示

偏移值为0，反应data值

偏移值为4，反应data MASK

偏移值为8，反应DIR方向

 

/* registers definitions for GPIO controller */

#define REG_GPIO_DATA (0x0000)

#define REG_GPIO_DMSK (0x0004)

#define REG_GPIO_DIR (0x0008) /* only for gpio */

#define REG_GPIO_IS (0x000c) /* only for gpio */

#define REG_GPIO_IBE (0x0010) /* only for gpio */

#define REG_GPIO_IEV (0x0014)

#define REG_GPIO_IE (0x0018)

#define REG_GPIO_RIS (0x001c)

#define REG_GPIO_MIS (0x0020)

#define REG_GPIO_IC (0x0024)

#define REG_GPIO_INEN (0x0028) /* only for gpio */

0x0000

GPIODATA

GPIO bits data

0x0004

GPIODMSK

GPIO bits data mask

0x0008

GPIODIR

GPIO bits data direction

0x000C

GPIOIS

GPIO bits interrupt sense

0x0010

GPIOIBE

GPIO bits both edges interrupt

0x0014

GPIOIEV

GPIO bits interrupt event

0x0018

GPIOIE

GPIO bits interrupt enable

0x001C

GPIORIS

GPIO bits raw interrupt status

0x0020

GPIOMIS

GPIO bits masked interrupt status

0x0024

GPIOIC

GPIO bits interrupt clear

0x0028

GPIOINEN

GPIO input enable

 

 

展讯平台gpio配置

 

展讯平台gpio配置

GPIODATA寄存器，可以反映出gpio bits data input

 

 

展讯平台gpio配置

 

 

展讯平台gpio配置

 

展讯平台gpio配置

 

展讯平台gpio配置

 

展讯平台gpio配置

展讯平台gpio配置

展讯平台gpio配置

 

 

 

展讯平台gpio配置

 

展讯平台gpio配置

 

展讯平台gpio配置

3 上下拉 驱动电流的控制

展讯平台gpio配置

 

DRV driver strength

WPUS pull up resistor select

SE schmitt trigger input enable

WPU weakly pull up for function mode

WPDO weakly pull down for function mode

 

slp_WPU weak pull up control in chip deep sleep mode

slp_WPDO weak pull down control in chip deep sleep mode

PIN_NAME_slp_ie Input enable control in chip deep sleep mode

PIN_NAME_slp_oe Output enable control in chip deep sleep mode

 

PIN_NAME_slp_en

Sleep mode enable:

BIT0: Sleep with AP sleep

BIT1: Sleep with PUBCP sleep

BIT2: Sleep with WTLCP sleep

BIT3: Sleep with WCN sleep

BIT4: Sleep with CM4 sleep

 

#define BIT_PIN_SLP_CM4 ( BIT_17 )

#define BIT_PIN_SLP_WCN ( BIT_16 )

#define BIT_PIN_SLP_WTLCP ( BIT_15 )

#define BIT_PIN_SLP_PUBCP ( BIT_14 )

#define BIT_PIN_SLP_AP ( BIT_13 )

 

=========================================================

示例1

gpio32

模式的选择

/system/bin/r 0x402A01EC

402a01ec: 00000030 //表明设置的是GPIO模式

值和方向的控制

/system/bin/r 0x40280100 值

/system/bin/r 0x40280104 mask

/system/bin/r 0x40280108 direction

---------------------------------------------------

示例2

gpio31

模式的选择

/system/bin/r 0x402A01E8

402a01e8: 00000030 //表明设置的是GPIO模式

值和方向的控制

/system/bin/r 0x40280080 值

40280080: 00008000//表明为高电平

40280080: 00000000//表明为低电平

/system/bin/r 0x40280084 mask

/system/bin/r 0x40280088 direction

 

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