verilog阻塞与非阻塞的初步理解(二)

时间:2022-09-25 19:26:02

将阻塞模块改为下述代码:

module blocking(clk,a,b,c);
input[:] a;
input clk;
output[:] b,c;
reg[:] b,c; always @(posedge clk)
begin
c=b;
$display("blocking:a=%d,b=%d,c=%d.",a,b,c);
end always @(posedge clk)
begin
b=a;
$display("blocking:a=%d,b=%d,c=%d.",a,b,c);
end endmodule

仿真得出结果:

# ________________
# blocking:a= 3,b= x,c= x.
# blocking:a= 3,b= x,c= x.
# non_blocking:a= 3,b= x,c= x.
# ________________
# blocking:a= 7,b= 3,c= x.
# blocking:a= 7,b= 3,c= x.
# non_blocking:a= 7,b= 3,c= x.
# ________________
# blocking:a=15,b= 7,c= 3.
# blocking:a=15,b= 7,c= 3.
# non_blocking:a=15,b= 7,c= 3.
# ________________
# blocking:a=10,b=15,c= 7.
# blocking:a=10,b=15,c= 7.
# non_blocking:a=10,b=15,c= 7.
# ________________
# blocking:a= 2,b=10,c=15.
# blocking:a= 2,b=10,c=15.
# non_blocking:a= 2,b=10,c=15.

若更改两个always 模块的先后顺序如下:

module blocking(clk,a,b,c);
input[:] a;
input clk;
output[:] b,c;
reg[:] b,c; always @(posedge clk)
begin
b=a;
$display("blocking:a=%d,b=%d,c=%d.",a,b,c);
end always @(posedge clk)
begin
c=b;
$display("blocking:a=%d,b=%d,c=%d.",a,b,c);
end endmodule

则会得到结果:

# ________________
# blocking:a= 3,b= 3,c= x.
# blocking:a= 3,b= 3,c= 3.
# non_blocking:a= 3,b= x,c= x.
# ________________
# blocking:a= 7,b= 7,c= 3.
# blocking:a= 7,b= 7,c= 7.
# non_blocking:a= 7,b= 3,c= x.
# ________________
# blocking:a=15,b=15,c= 7.
# blocking:a=15,b=15,c=15.
# non_blocking:a=15,b= 7,c= 3.
# ________________
# blocking:a=10,b=10,c=15.
# blocking:a=10,b=10,c=10.
# non_blocking:a=10,b=15,c= 7.
# ________________
# blocking:a= 2,b= 2,c=10.
# blocking:a= 2,b= 2,c= 2.
# non_blocking:a= 2,b=10,c=15.

可以看出alway模块的先后顺序会影响b,c的取值。理论上,两个模块是并行执行的,他们出现的先后顺序并不会影响最终得到的结果。

但从这里看出,其是有先后顺序的。只是不知道是仿真器的顺序执行的原因还是竞争冒险导致的。

不过这种情况在非阻塞赋值时不会出现,非阻塞赋值结果是一致的。