![](https://image.shishitao.com:8440/aHR0cHM6Ly9pbWFnZXMuY25ibG9ncy5jb20vT3V0bGluaW5nSW5kaWNhdG9ycy9Db250cmFjdGVkQmxvY2suZ2lm.gif?w=700)
1 module D_flop(data,clk,clr,q,qb); 2 input data,clk,clr; 3 output q,qb; 4 wire a,b,c,d,e,f,ndata,nclk; 5 nand nand1(a,clr,data,clk), 6 nand2(b,ndata,clk), 7 nand4(d,c,b,clr), 8 nand5(e,c,nclk), 9 nand6(f,d,nclk), 10 nand8(qb,f,clr,q); 11 nand nand3(c,a,d), 12 nand7(q,e,qb); 13 not not1(ndata,data), 14 not2(nclk,clk); 15 endmodule
上图就是门级Verilog语言描述的对应的网表,由图可以看出这是一个带异步置零的D触发器。
同样我们也可以采用行为描述来定义D触发器。
普通D触发器:
![](https://image.shishitao.com:8440/aHR0cHM6Ly9pbWFnZXMuY25ibG9ncy5jb20vT3V0bGluaW5nSW5kaWNhdG9ycy9Db250cmFjdGVkQmxvY2suZ2lm.gif?w=700)
1 module D_EF(Q,D,CLK) 2 input D,CLK; 3 output Q; 4 reg Q; //在always语句中被赋值的信号要声明为reg类型寄存器定义 5 always @ (posedge CLK) 6 begin Q <= D; end 7 endmodule
异步D触发器:
![](https://image.shishitao.com:8440/aHR0cHM6Ly9pbWFnZXMuY25ibG9ncy5jb20vT3V0bGluaW5nSW5kaWNhdG9ycy9Db250cmFjdGVkQmxvY2suZ2lm.gif?w=700)
1 module D_EF(q,qn,d,clk,set,reset) 2 input d,clk,set,reset; 3 output q,qn; 4 reg q,qn; //寄存器定义 5 always @ (posedge clk or negedge set or negedge reset) 6 begin 7 if(!reset) begin q<=0;qn<=1;end//异步清0,低有效 8 else if(!set) begin q<=1;qn<=1;end //异步置1,低有效 9 else begin q<=~d;qn<=~d;end 10 end 11 endmodule
同步触发器:
![](https://image.shishitao.com:8440/aHR0cHM6Ly9pbWFnZXMuY25ibG9ncy5jb20vT3V0bGluaW5nSW5kaWNhdG9ycy9Db250cmFjdGVkQmxvY2suZ2lm.gif?w=700)
1 module D_EF(q,qn,d,clk,set,reset) 2 input d,clk,set,reset; 3 output q,qn; 4 reg q,qn; 5 always @ (posedge clk) 6 begin 7 if(!reset) begin q<=0;qn<=1;end//同步清0,低有效 8 else if(!set) begin q<=1;qn<=1;end //同步置1,低有效 9 else begin q<=~d;qn<=~d;end 10 end 11 endmodule
注意,异步和同步触发器中else begin q<=~d;qn<=~d;end 更正为else begin q<=d;qn<=~d;end
![](https://image.shishitao.com:8440/aHR0cHM6Ly9pbWcyMDIyLmNuYmxvZ3MuY29tL2Jsb2cvMzU2OTUvMjAyMjAxLzM1Njk1LTIwMjIwMTIwMTgzMDM4MDczLTE4MDg2MzE3Ny5qcGc%3D.jpg?w=700)