参考博文：http://blog.sina.com.cn/s/blog_5ced60e80102y7pd.html
一颗健壮的IC芯片应该具有能屈能伸的品质，他需要适应于他所在应用范围内变化的温度、电压，他需要承受制造工艺的偏差，这就需要在设计实现过程中考虑这些变化的温度、电压和工艺偏差。
在STA星球，用library PVT、RC corner跟OCV来模拟这些不可控的随机因素。在每个工艺结点，通过大量的建模跟实测，针对每个具体的工艺，foundary厂都会提供一张推荐的timingsignoff表格， 建议需要signoff的corner及各个corner需要设置的ocv跟margin。这些corner能保证大部分芯片可以承受温度、电压跟工艺偏差，一个corner=libraryPVT+ RC corner + OCV，本文将关注于library PVT。
P-process：IC制造工艺本身的不完美，使得制造偏差不可避免，在library中会用一个百分比来表示工艺偏差，如process:1表示没偏差。在沉积或参杂过程中，杂质浓度密度、氧化层厚度、扩散深度都可能发生偏差，从而导致管子的电阻跟阈值电压发生偏差；光刻过程中由于分辨率的偏差会导致管子的宽长比产生偏差。而这些偏差，都会导致管子性能的差异。
Network电容：
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耦合电容：Coupling capacitance=e*T/S
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表面电容：Surface capcitance=e*W/H
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边缘电容：Fringe capcitance
决定容值的因素：
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介电常数：e
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线宽：W
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线厚：T
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线间距：S
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介电材料的厚度：H
随着工艺进步，W, S, T 逐代递减，表面电容跟随减小，耦合电容随之增加，耦合电容在总电容中占比增加，当线厚 T 一定时为了减少耦合电容要么增加线间距要么减小介电常数。通常为了减小噪声敏感信号线（如clock net）上的耦合电容，在物理实现时会人为增加对应信号的线宽及线间距，俗称NDR。要减小介电常数需要从材料入手，从 .18开始引入low K介电材料。
Network电阻：
R=r/W*T, r为电阻率，除了跟线宽 W 和线厚 T 相关之外，还跟温度相关，随着温度的上升而增大。
|
Parameters |
Resistance |
Surface Capacitance |
Coupling Capacitance |
|
温度增加 |
增加 |
-- |
-- |
|
线宽减小 |
增加 |
减小 |
-- |
|
线厚减小 |
增加 |
-- |
减小 |
|
线间距减小 |
无影响 |
无影响 |
增加 |
由上面的分析可知，Network的单位电容和单位电阻是不可能同时最大或同时最小的。有了这些铺垫，来看一下不同工艺结点是如何定义RC corner的。
90nm 之前，Cell delay占主导，Network电容主要是对地电容，STA只需要两个RC corner即可：
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Cbest(Cmin): 电容最小电阻最大
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Cworst(Cmax):电容最大电阻最小
90nm 之后，netdelay的比重越来越大，而且network的耦合电容不可忽略，所以又增加了两个RC corner:
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RCbest(XTALK corner): 耦合电容最大，（对地电容*电阻）最小
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RCworst(Delay corner): 耦合电容最小，（对地电容*电阻）最大
至此总共有两个需要setup timing sign-off的RC corner，有四个需要hold timing sign-off的RC corner：
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Setup time sign-off 的RC corner是: Cworst / RCworst
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Hold time sign-off 的RC corner是: Cbest / RCbest / Cworst / RCworst
C-best:
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It hasminimum capacitance. So also known as Cmin corner.
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Interconnect Resistance is larger than the Typical corner.
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This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.
C-worst:
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Refers tocorners which results maximum Capacitance. So also known as Cmax corner.
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Interconnect resistance is smaller than at typical corner.
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This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.
RC-best:
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Refers tothe corners which minimize interconnect RC product. So also known as RC-mincorner.
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Typicallycorresponds to smaller etch which increases the trace width. This results insmallest resistance but corresponds to larger than typical capacitance.
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Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.
RC-worst:
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Refers tothe corners which maximize interconnect RC product. So also known as RC-maxcorner.
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Typicallycorresponds to larger etch which reduces the trace width. This results inlargest resistance but corresponds to smaller than typical capacitance.
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Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.
------C = a * W *L R = b *L/W RC = ab * L^2
所以对于短线来说（L很小），RC由于与L的平方成正比，非常小，电容起主要作用。对于长线RC起主要作用。
引入的DPT（Double Patterning Technology）之后，在同一层layer上要做两次mask，两次mask之间的偏差，会导致线间距变化，从而影响耦合电容值，需要将这一因素考虑到RC corner中，所以DPT 的RC corner是：Cworst_CCworst, RCworst_CCworst, Cbest_CCbest, RCbest_CCbest.
其中：
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Setup timesign-off 的RC corner是: Cworst_CCworst / RCworst_CCworst
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Hold timesign-off 的RC corner是: Cbest_CCbest / RCbest_CCbest / Cworst_CCworst /RCworst_CCworst
除以上这些corner外，还有一个corner叫Typical corner，对应于DPT的是Ctypical_CCworst, Ctypical_CCbest，这些corner不用于timing sign-off。
Q：还有一种RC corner 带后缀『_T』，只用于setup signoff，T指的是什么？
A：T代表tighten，在rc的variation上的sigma分布比不带T的更紧，因此只能用于setup，hold不推荐。Appleto Apple地比较，T的variation更小，理论看到的rc变化更小，单从setup产生violation的可能性更小。至于悲观还是乐观，除非自己定criteria，其余的follow foundry或者vendor的rule最重要。
Q：为什么setup既需要sign-off C-corner又需要sign-offRC-corner？
A：因为C-corner表示『电容』最大/最小，而RC-corner是『电容*电阻』最大/最小。通常对于短线而言，电容占主导地位，C-corner可以cover RC-corner，但对于长线则电阻占主导地位，C-corner无法cover RC-corner，而是反过来RC-corner去cover C-corner。而没人保证一个设计里只有短线没有长线，也没权威对长短的幅度有量化的定义，所以最保险的就是两者分别sign-off。
Q：为什么hold需要sign-off所有的corner？
A：对于hold而言，根据其仿真曲线，相互之间都无法完全覆盖，故需要sign-off所有corner。
Q：金属电阻是否跟density/spacing相关？为什么方块电阻跟density/spacing相关？
A：就电阻本身而言，阻值跟density没有关系，只跟金属线自身的宽厚和电阻率相关，详细描述：
There is no relationship between the density of a metal and itselectrical resistivity.
There is a big database of material properties called MatWeb which is recommend as a legitimate source of data by UCSD\'s and Stanford\'s library systems, Rose-Hulman, etc. I took data fromaround 60 different metals and graphed them:
As you can see there is no empirical relationship. From a theoryperspective, density has to do with atomic packing and resistivity has to dowith electronic structure.
Iwill admit, however, that gaseous copper is an extremely poor conductor.
但是，在半导*造过程中，由于工艺偏差，电阻跟金属线的density是相关的。此时，电阻率是线宽跟线间距的函数。这一关系，在foundry给的工艺文件里都有相应的描述，这些都是在抽RC时需要考虑的因素。
Resistivity as a Function of Width and Spacing (Rs = f(W) or rho=f(W,S))
Variationin resistivity is caused by a number of phenomena. Copper is a softer materialthan the dielectric in which it is embedded. As a result, the polishing of thewafer during the CMP process has a tendency to remove a little extra copperfrom the top of the wire. This effect is called dishing because of the shape ofthe resulting wire top. The effect becomes more pronounced as the wire widthincreases. This effect is shown in exaggerated form in following pic.
To reduce theeffect of dishing on wide wires, small holes, or slots, can be inserted atregular intervals in wide wires. These slots insert a form of hard"posts" in the wire so that the CMP process removes less copper. Thistechnique reduces the dishing, as well as the effective resistivity.
Anothercontributor to resistivity variation is the cladding in copper wires. Claddingis the material grown around the sides and bottom of copper wires to protectthem from chemical reactions with the dielectric material. This cladding isillustrated in gray in following pic. The thickness ofthe cladding on the sides and bottoms of wires also varies with the width of awire. Because cladding has a much higher resistance than copper, it impacts theeffective resistivity of copper wires. This effect is more pronounced in thenarrowest wires. The combination of the effects ofdishing, slotting, and cladding thickness is modeled by the wire resistivity asa function of the wire width in silicon, and its spacing.
Q：在《抽刀断水水更流，RC Corner不再愁：STA之RC Corner》中说电阻跟spacing无关，在《一曲新词酒一杯，RC Corner继续飞: STA之RC Corner拾遗》又说电阻跟spacing有关，为什么电阻跟spacing就相关了？
A：就电阻本身是跟spacing没有无关的，但在半导*造过程中，因为铜软，所以在dishing时会把铜线切掉一些，这跟那个范围的金属线密度相关，而且这个关系好像也不是线性的。线的密度不同，会使得制造过程对线的厚度造成的影响不同，线厚度被改变了，那阻值自然被改变了。在QRC抽RC的时候会把这一效应模拟成『电阻率=f(W,S)』。 这一效应在foundry给的工艺文件里有相应的描述。
@SteveB 后端角度？如果讲RC 后端抽怎么考虑，讲好原理以后剩下的就是按照RC corner 加上温度抽，交给工具。如果想要知道原理，有几个方面可以去考虑，也是一般后端拿到新工艺需要去研究的:
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对于寄生参数提取，相关的各个工具的技术文件怎么来？
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每个corner下的配合PVT signoff里的T趋势如何，是否可以对signoff做精简 ？
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double pattern multiple pattern 的影响如何？
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研究DFM。
当然还有其他，我这里想到比较能自己去学的有这些。
Q：通常说的ttcorner指的是啥？
A：@孟时光 ttcorner是指管子在tt+RCtyp吧。
Types of corners
When working in the schematic domain, we usually only work with front end of line (FEOL) process corners as these corners will affect the performance of devices. But there is an orthogonal set of process parameters that affect back end of line (BEOL) parasitics.
FEOL corners
One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS)corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal,respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.
There are therefore five possible corners:typical-typical (TT) (not really a corner of an n vs. p mobility graph, butcalled a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), andslow-fast (SF). The first three corners (TT, FF, SS) are called even corners,because both types of devices are affected evenly, and generally do notadversely affect the logical correctness of the circuit. The resulting devicescan function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed"corners, and are cause for concern. This is because one type of FET will switchmuch faster than the other, and this form of imbalanced switching can cause oneedge of the output to have much less slew than the other edge. Latching devices may then record incorrect values in the logic chain.
BEOL corners
In addition to the FETs themselves, there are more on-chip variation (OCV) effects that manifest themselves at smaller technology nodes. These include process, voltage and temperature (PVT) variation effects on on-chip interconnect, as well as via structures.
Extraction tools often have a nominal corner to reflect the nominal cross section of the process target.Then the corners cbest and cworst were created to model the smallest and largest cross sections that are in the allowed process variation. A simple thought experiment shows that the smallest cross section with the largest vertical spacing will produce the smallest coupling capacitance. CMOS Digital circuits were more sensitive to capacitance than resistance so this variation was initially acceptable. As processes evolved and resistance of wiring became more critical, the additional rcbest and rcworst were created to model the minimum and maximum cross sectional areas for resistance.But the one change is that cross sectional resistance is not dependent on oxide thickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.
Parameters
Most importantly, the corners of a process are designated by five parameters
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Mobility variation due to implantation of N+ and P+
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Vth variation
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Resistance of the actives
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Body coefficient
-
Oxide thickness
Other parameters like the effective Length, effective width, Cjsw caps, Cj caps also change.
注：所以TT corner并不是一个需要sign-off的corner。