Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA
Motivation
To address the slow operation and high energy and resource consumption problem caused by realizing spiking neural network (SNN) using software.
Problem
- software : slow operation, high energy consumption and space resources
- analog circuits: hard to reconfigure and intrinsically sensitive to process, voltage and temperature (PVT) Var.
- FPGA: most of works focus on the acceleration of SNN without considering energy consumption and efficiency of resource utilization.
- This work presented the parallel neuromorphic processor architectures with approximate arithmetic for SNN on FPGA.
Related work
There is no related work part in this paper.
In-Datacenter Performance Analysis of a Tensor Processing Unit
Motivation
This paper evaluates a custom ASIC - called a Tensor Processing Unit (TPU) to accelerates the inference phase of neural networks (NN).
Problem
Many NN applications have hard response time deadline. Hence, inference phase must response quickly when user do some action. While CPU and GPU are poor in response.
Related work
All works are focus on hardware processing, such as DRAM, hardware protocol and so on.