WARN::_complete:272: Unknown urb status -685060256, but assumed to be an EPROTO
Bulk In Failed. Status=-71, BIIdx=0x4, BIRIdx=0x4, actual_length= 0x5e8
这没什么太大的关系，但测试的时候，过一段时间就会出现不过打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
6 个解决方案
#1
看上去没什么错误
#2
打错字了，
这没什么太大的关系，但测试的时候，过一段时间就会出现不过打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
是过一段时间就会不停打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
这没什么太大的关系，但测试的时候，过一段时间就会出现不过打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
是过一段时间就会不停打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
#3
这是USB的错误呢
看一下源码
看一下源码
/**
1594 * Handles a host Channel Halted interrupt in DMA mode. This handler
1595 * determines the reason the channel halted and proceeds accordingly.
1596 */
1597 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1598 dwc_hc_t *hc,
1599 dwc_otg_hc_regs_t *hc_regs,
1600 dwc_otg_qtd_t *qtd)
1601 {
1602 hcint_data_t hcint;
1603 hcintmsk_data_t hcintmsk;
1604 int out_nak_enh = 0;
1605
1606 /* For core with OUT NAK enhancement, the flow for high-
1607 * speed CONTROL/BULK OUT is handled a little differently.
1608 */
1609 if (hcd->core_if->snpsid >= 0x4F54271A) {
1610 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1611 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1612 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1613 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
1614 out_nak_enh = 1;
1615 } else {
1616 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1617 }
1618 } else {
1619 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
1620 }
1621
1622 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1623 hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1624 /*
1625 * Just release the channel. A dequeue can happen on a
1626 * transfer timeout. In the case of an AHB Error, the channel
1627 * was forced to halt because there's no way to gracefully
1628 * recover.
1629 */
1630 release_channel(hcd, hc, qtd, hc->halt_status);
1631 return;
1632 }
1633
1634 /* Read the HCINTn register to determine the cause for the halt. */
1635 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1636 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1637
1638 if (hcint.b.xfercomp) {
1639 /** @todo This is here because of a possible hardware bug. Spec
1640 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1641 * interrupt w/ACK bit set should occur, but I only see the
1642 * XFERCOMP bit, even with it masked out. This is a workaround
1643 * for that behavior. Should fix this when hardware is fixed.
1644 */
1645 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1646 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1647 }
1648 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1649 } else if (hcint.b.stall) {
1650 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1651 } else if (hcint.b.xacterr) {
1652 if (out_nak_enh) {
1653 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1654 printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
1655 qtd->error_count = 0;
1656 } else {
1657 printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
1658 }
1659 }
1660
1661 /*
1662 * Must handle xacterr before nak or ack. Could get a xacterr
1663 * at the same time as either of these on a BULK/CONTROL OUT
1664 * that started with a PING. The xacterr takes precedence.
1665 */
1666 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1667 } else if (!out_nak_enh) {
1668 if (hcint.b.nyet) {
1669 /*
1670 * Must handle nyet before nak or ack. Could get a nyet at the
1671 * same time as either of those on a BULK/CONTROL OUT that
1672 * started with a PING. The nyet takes precedence.
1673 */
1674 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1675 } else if (hcint.b.bblerr) {
1676 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1677 } else if (hcint.b.frmovrun) {
1678 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1679 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1680 /*
1681 * If nak is not masked, it's because a non-split IN transfer
1682 * is in an error state. In that case, the nak is handled by
1683 * the nak interrupt handler, not here. Handle nak here for
1684 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1685 * rewinding the buffer pointer.
1686 */
1687 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1688 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1689 /*
1690 * If ack is not masked, it's because a non-split IN transfer
1691 * is in an error state. In that case, the ack is handled by
1692 * the ack interrupt handler, not here. Handle ack here for
1693 * split transfers. Start splits halt on ACK.
1694 */
1695 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1696 } else {
1697 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1698 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1699 /*
1700 * A periodic transfer halted with no other channel
1701 * interrupts set. Assume it was halted by the core
1702 * because it could not be completed in its scheduled
1703 * (micro)frame.
1704 */
1705 #ifdef DEBUG
1706 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1707 __func__, hc->hc_num);
1708 #endif
1709 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1710 } else {
1711 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1712 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1713 __func__, hc->hc_num, hcint.d32,
1714 dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
1715 }
1716 }
1717 } else {
1718 printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
1719 }
1720 }
#4
这是USB的错误呢
看一下源码
看一下源码
/**
1594 * Handles a host Channel Halted interrupt in DMA mode. This handler
1595 * determines the reason the channel halted and proceeds accordingly.
1596 */
1597 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1598 dwc_hc_t *hc,
1599 dwc_otg_hc_regs_t *hc_regs,
1600 dwc_otg_qtd_t *qtd)
1601 {
1602 hcint_data_t hcint;
1603 hcintmsk_data_t hcintmsk;
1604 int out_nak_enh = 0;
1605
1606 /* For core with OUT NAK enhancement, the flow for high-
1607 * speed CONTROL/BULK OUT is handled a little differently.
1608 */
1609 if (hcd->core_if->snpsid >= 0x4F54271A) {
1610 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1611 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1612 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1613 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
1614 out_nak_enh = 1;
1615 } else {
1616 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1617 }
1618 } else {
1619 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
1620 }
1621
1622 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1623 hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1624 /*
1625 * Just release the channel. A dequeue can happen on a
1626 * transfer timeout. In the case of an AHB Error, the channel
1627 * was forced to halt because there's no way to gracefully
1628 * recover.
1629 */
1630 release_channel(hcd, hc, qtd, hc->halt_status);
1631 return;
1632 }
1633
1634 /* Read the HCINTn register to determine the cause for the halt. */
1635 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1636 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1637
1638 if (hcint.b.xfercomp) {
1639 /** @todo This is here because of a possible hardware bug. Spec
1640 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1641 * interrupt w/ACK bit set should occur, but I only see the
1642 * XFERCOMP bit, even with it masked out. This is a workaround
1643 * for that behavior. Should fix this when hardware is fixed.
1644 */
1645 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1646 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1647 }
1648 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1649 } else if (hcint.b.stall) {
1650 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1651 } else if (hcint.b.xacterr) {
1652 if (out_nak_enh) {
1653 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1654 printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
1655 qtd->error_count = 0;
1656 } else {
1657 printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
1658 }
1659 }
1660
1661 /*
1662 * Must handle xacterr before nak or ack. Could get a xacterr
1663 * at the same time as either of these on a BULK/CONTROL OUT
1664 * that started with a PING. The xacterr takes precedence.
1665 */
1666 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1667 } else if (!out_nak_enh) {
1668 if (hcint.b.nyet) {
1669 /*
1670 * Must handle nyet before nak or ack. Could get a nyet at the
1671 * same time as either of those on a BULK/CONTROL OUT that
1672 * started with a PING. The nyet takes precedence.
1673 */
1674 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1675 } else if (hcint.b.bblerr) {
1676 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1677 } else if (hcint.b.frmovrun) {
1678 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1679 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1680 /*
1681 * If nak is not masked, it's because a non-split IN transfer
1682 * is in an error state. In that case, the nak is handled by
1683 * the nak interrupt handler, not here. Handle nak here for
1684 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1685 * rewinding the buffer pointer.
1686 */
1687 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1688 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1689 /*
1690 * If ack is not masked, it's because a non-split IN transfer
1691 * is in an error state. In that case, the ack is handled by
1692 * the ack interrupt handler, not here. Handle ack here for
1693 * split transfers. Start splits halt on ACK.
1694 */
1695 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1696 } else {
1697 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1698 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1699 /*
1700 * A periodic transfer halted with no other channel
1701 * interrupts set. Assume it was halted by the core
1702 * because it could not be completed in its scheduled
1703 * (micro)frame.
1704 */
1705 #ifdef DEBUG
1706 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1707 __func__, hc->hc_num);
1708 #endif
1709 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1710 } else {
1711 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1712 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1713 __func__, hc->hc_num, hcint.d32,
1714 dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
1715 }
1716 }
1717 } else {
1718 printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
1719 }
1720 }
#6
看到头都晕了，还是不知道怎么解决……杯具呀……
#1
看上去没什么错误
#2
打错字了，
这没什么太大的关系，但测试的时候，过一段时间就会出现不过打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
是过一段时间就会不停打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
这没什么太大的关系，但测试的时候，过一段时间就会出现不过打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
是过一段时间就会不停打印以下语句,造成死机：
NYET/NAK/ACK/other in non-error case, 0x00000002
#3
这是USB的错误呢
看一下源码
看一下源码
/**
1594 * Handles a host Channel Halted interrupt in DMA mode. This handler
1595 * determines the reason the channel halted and proceeds accordingly.
1596 */
1597 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1598 dwc_hc_t *hc,
1599 dwc_otg_hc_regs_t *hc_regs,
1600 dwc_otg_qtd_t *qtd)
1601 {
1602 hcint_data_t hcint;
1603 hcintmsk_data_t hcintmsk;
1604 int out_nak_enh = 0;
1605
1606 /* For core with OUT NAK enhancement, the flow for high-
1607 * speed CONTROL/BULK OUT is handled a little differently.
1608 */
1609 if (hcd->core_if->snpsid >= 0x4F54271A) {
1610 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1611 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1612 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1613 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
1614 out_nak_enh = 1;
1615 } else {
1616 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1617 }
1618 } else {
1619 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
1620 }
1621
1622 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1623 hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1624 /*
1625 * Just release the channel. A dequeue can happen on a
1626 * transfer timeout. In the case of an AHB Error, the channel
1627 * was forced to halt because there's no way to gracefully
1628 * recover.
1629 */
1630 release_channel(hcd, hc, qtd, hc->halt_status);
1631 return;
1632 }
1633
1634 /* Read the HCINTn register to determine the cause for the halt. */
1635 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1636 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1637
1638 if (hcint.b.xfercomp) {
1639 /** @todo This is here because of a possible hardware bug. Spec
1640 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1641 * interrupt w/ACK bit set should occur, but I only see the
1642 * XFERCOMP bit, even with it masked out. This is a workaround
1643 * for that behavior. Should fix this when hardware is fixed.
1644 */
1645 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1646 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1647 }
1648 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1649 } else if (hcint.b.stall) {
1650 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1651 } else if (hcint.b.xacterr) {
1652 if (out_nak_enh) {
1653 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1654 printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
1655 qtd->error_count = 0;
1656 } else {
1657 printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
1658 }
1659 }
1660
1661 /*
1662 * Must handle xacterr before nak or ack. Could get a xacterr
1663 * at the same time as either of these on a BULK/CONTROL OUT
1664 * that started with a PING. The xacterr takes precedence.
1665 */
1666 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1667 } else if (!out_nak_enh) {
1668 if (hcint.b.nyet) {
1669 /*
1670 * Must handle nyet before nak or ack. Could get a nyet at the
1671 * same time as either of those on a BULK/CONTROL OUT that
1672 * started with a PING. The nyet takes precedence.
1673 */
1674 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1675 } else if (hcint.b.bblerr) {
1676 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1677 } else if (hcint.b.frmovrun) {
1678 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1679 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1680 /*
1681 * If nak is not masked, it's because a non-split IN transfer
1682 * is in an error state. In that case, the nak is handled by
1683 * the nak interrupt handler, not here. Handle nak here for
1684 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1685 * rewinding the buffer pointer.
1686 */
1687 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1688 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1689 /*
1690 * If ack is not masked, it's because a non-split IN transfer
1691 * is in an error state. In that case, the ack is handled by
1692 * the ack interrupt handler, not here. Handle ack here for
1693 * split transfers. Start splits halt on ACK.
1694 */
1695 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1696 } else {
1697 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1698 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1699 /*
1700 * A periodic transfer halted with no other channel
1701 * interrupts set. Assume it was halted by the core
1702 * because it could not be completed in its scheduled
1703 * (micro)frame.
1704 */
1705 #ifdef DEBUG
1706 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1707 __func__, hc->hc_num);
1708 #endif
1709 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1710 } else {
1711 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1712 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1713 __func__, hc->hc_num, hcint.d32,
1714 dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
1715 }
1716 }
1717 } else {
1718 printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
1719 }
1720 }
#4
这是USB的错误呢
看一下源码
看一下源码
/**
1594 * Handles a host Channel Halted interrupt in DMA mode. This handler
1595 * determines the reason the channel halted and proceeds accordingly.
1596 */
1597 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1598 dwc_hc_t *hc,
1599 dwc_otg_hc_regs_t *hc_regs,
1600 dwc_otg_qtd_t *qtd)
1601 {
1602 hcint_data_t hcint;
1603 hcintmsk_data_t hcintmsk;
1604 int out_nak_enh = 0;
1605
1606 /* For core with OUT NAK enhancement, the flow for high-
1607 * speed CONTROL/BULK OUT is handled a little differently.
1608 */
1609 if (hcd->core_if->snpsid >= 0x4F54271A) {
1610 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1611 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1612 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1613 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
1614 out_nak_enh = 1;
1615 } else {
1616 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1617 }
1618 } else {
1619 DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
1620 }
1621
1622 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1623 hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1624 /*
1625 * Just release the channel. A dequeue can happen on a
1626 * transfer timeout. In the case of an AHB Error, the channel
1627 * was forced to halt because there's no way to gracefully
1628 * recover.
1629 */
1630 release_channel(hcd, hc, qtd, hc->halt_status);
1631 return;
1632 }
1633
1634 /* Read the HCINTn register to determine the cause for the halt. */
1635 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1636 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1637
1638 if (hcint.b.xfercomp) {
1639 /** @todo This is here because of a possible hardware bug. Spec
1640 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1641 * interrupt w/ACK bit set should occur, but I only see the
1642 * XFERCOMP bit, even with it masked out. This is a workaround
1643 * for that behavior. Should fix this when hardware is fixed.
1644 */
1645 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1646 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1647 }
1648 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1649 } else if (hcint.b.stall) {
1650 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1651 } else if (hcint.b.xacterr) {
1652 if (out_nak_enh) {
1653 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1654 printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
1655 qtd->error_count = 0;
1656 } else {
1657 printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
1658 }
1659 }
1660
1661 /*
1662 * Must handle xacterr before nak or ack. Could get a xacterr
1663 * at the same time as either of these on a BULK/CONTROL OUT
1664 * that started with a PING. The xacterr takes precedence.
1665 */
1666 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1667 } else if (!out_nak_enh) {
1668 if (hcint.b.nyet) {
1669 /*
1670 * Must handle nyet before nak or ack. Could get a nyet at the
1671 * same time as either of those on a BULK/CONTROL OUT that
1672 * started with a PING. The nyet takes precedence.
1673 */
1674 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1675 } else if (hcint.b.bblerr) {
1676 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1677 } else if (hcint.b.frmovrun) {
1678 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1679 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1680 /*
1681 * If nak is not masked, it's because a non-split IN transfer
1682 * is in an error state. In that case, the nak is handled by
1683 * the nak interrupt handler, not here. Handle nak here for
1684 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1685 * rewinding the buffer pointer.
1686 */
1687 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1688 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1689 /*
1690 * If ack is not masked, it's because a non-split IN transfer
1691 * is in an error state. In that case, the ack is handled by
1692 * the ack interrupt handler, not here. Handle ack here for
1693 * split transfers. Start splits halt on ACK.
1694 */
1695 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1696 } else {
1697 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1698 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1699 /*
1700 * A periodic transfer halted with no other channel
1701 * interrupts set. Assume it was halted by the core
1702 * because it could not be completed in its scheduled
1703 * (micro)frame.
1704 */
1705 #ifdef DEBUG
1706 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1707 __func__, hc->hc_num);
1708 #endif
1709 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1710 } else {
1711 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1712 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1713 __func__, hc->hc_num, hcint.d32,
1714 dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
1715 }
1716 }
1717 } else {
1718 printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
1719 }
1720 }
#5
#6
看到头都晕了，还是不知道怎么解决……杯具呀……