实验现象：
打开tool-->Netlist viewer-->RTL viewer可观察各个逻辑连接
核心代码：
//--------------------module_logic_gates---------------------//
module logic_gates(
input clk_25m,
output c,
output d,
output e,
output f,
output g,
output h,
output i,
output j,
output k,
output l
);
//--------------------logic_gates_ctrl----------------------//
reg [9:0]b; //产生输入信号b
always@(posedge clk_25m)
if(b == 10'd1000)
b <= 10'd0;
else b <= b + 1'd1;
reg [7:0]a; //产生输入信号a
always@(posedge clk_25m)
if(a == 8'd500)
a <= 8'd0;
else a <= a + 1'd1;
assign c = a[7] && b[9]; //逻辑与
assign d = a[7] || b[9]; //逻辑或
assign e = !a[7]; //逻辑非
assign f = a[7] & b[9]; //按位与
assign g = a[7] | b[9]; //按位或
assign h = ~a[7]; //按位非
assign i = a[7] &~ b[9]; //按位与非
assign j = a[7] |~ b[9]; //按位或非
assign k = a[7] ^ b[9]; //按位异或
assign l = a[7] ~^ b[9]; //按位同或
//--------------------endmodule---------------------------//
endmodule
源代码下载链接：
链接：http://pan.baidu.com/s/1mi5fZy4 密码：mqcz
iCore4链接：
