Abstract DE2-70初學者常常會遇到這個錯誤訊息，在(原創) 如何解決DE2-70的『Error: Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』的錯誤訊息? (SOC) (Quartus II) (DE2-70)曾經討論過解決方式，不過當時並有解釋為什麼要這樣解(因為我當時也不懂)，本文重新徹底討論之。
Introduction 使用環境：Quartus II 10.1 + DE2-70 (Cyclone II EP 2C70F896CN)
本文將討論以下主題：
1.『Error：Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』錯誤訊息的意義。
2. 什麼是Dual-Purpose Pin?
3.什麼是nCEO?
4.如何使用Quartus II GUI將nCEO設定成regular I/O pin?
5.如何使用Tcl將nCEO設定成regular I/O pin?
『Error：Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』錯誤訊息的意義
在DE2-70，若用到SW[7]，根據[1] DE2-70 User Manual v1.08，在pin assignment時會指定到PIN_AD25。
在編譯時，一定會遇到以下錯誤訊息：
在(原創) 如何解決DE2-70的『Error: Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』的錯誤訊息? (SOC) (Quartus II) (DE2-70)曾經討論過解決方式，基本上只要跟著做就可以解決問題，不過當初並沒有解釋為什麼要這樣做。
根據Quartus II的Help的解釋如下：
Can't place multiple pins assigned to pin location <name> (<name>)
-------------------------------------------------------------------------------- CAUSE: You assigned two or more pins to the specified location, but the Fitter cannot place all the pins in that location. ACTION: If the conflict arises from location assignments in the current project, delete or change the location assignment of one or more of the pins. If the pin location assignments come from one or more imported design partitions, delete or change the location assignment (possibly using the Virtual Pin assignments) in the lower-level designs, re-generate the Quartus II Exported Partition File(s) (.qxp), and re-import.
大意就是你同時對Pin_AD25做了兩次的pin assignment，導致Fitter無法作P&R。
通常會遇到這個錯誤訊息，都是自己的pin assignment有寫錯，導致對同一根pin assign了兩次，不過在這裡，很顯然不是我們自己弄錯了。
根據[2] DE2-70 Schematic v1.1的電路圖
AD25除了SW7使用外，其實nCEO也使用這個pin，這也就是為什麼SW7會與nCEO都指定到Pin_AD25的原因了。
什麼是Dual-Purpose Pins?
根據[3] Quartus II Help, dual-purpose pins
Pins that can be used as I/O pins after initialization when configuring SRAM-based devices. The number of dual-purpose pins available in all Altera devices supported by the Quartus II software except MAX3000 and MAX7000 devices depends on the device's configuration scheme.
我們知道FPGA基本上是由SRAM所構成，使用前必須將*.sof檔program進FPGA後才可使用，所以FPGA保留了一些pin做programming用，一旦FPGA經過program之後，這些pin就可以拿來當一般的I/O pin使用，這些pin就是dual-purpose pin，之前所遇到的nCEO就是個dual-purpose pin。
什麼是nCEO?
根據[4] Cyclone III Device Family Pin Connection Guidelines對nCEO的description為
Output that drives low when device configuration is complete.
其connection guidelines為
During multi-device configuration, this pin feeds a subsequent device's nCE pin and must be pulled high to VCCIO by external10-KΩ pull-up resistor. During single device configuration and for the last device in multi-device configuration, this pin can be left floating or used as regular I/O after configuration.
nCE的定義為
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, device is disabled.
其connection guidelines為
In multi-device configuration, nCE of the first device is tied directly to GND while its nCEO pin drives the nCE of the next device in the chain. In single device configuration, nCE is tied directly to GND. The nCE pin must also be held low for successful JTAG programming of the device. If you are combining JTAG and AS configuration schemes, then the nCE should be tied to GND through a10-KΩ resistor.
大意是說，每顆FPGA都有nCE與nCEO兩根pin，在多顆FPGA的系統中，第一顆FPGA的nCE接GND，而第一顆FPGA的nCEO將接到下一顆FPGA的nCE，如此這樣繼續接下去，而在最後一顆FPGA時，可以將nCEO floating或者當成普通I/O pin使用。而在單顆FPGA時，nCE直接接GND，nCEO可直接floating或者當普通I/O pin使用。
在DE2-70，因為只是單顆FPGA，nCEO並沒有用到，所以當成SW[7]的input pin使用。
如何使用Quartus II GUI將nCEO設定成regular I/O pin?
如何使用Tcl將nCEO設定成regular I/O pin?
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION"USE AS REGULAR IO"
Conclusion 在[7] MyFPGA, DE0的VGA_B[0] Pin assignment有錯有人抱怨為什麼Quartus II要default將nCEO弄成programming pin，而非regular I/O pin，害我們自己必須手動改一次，其實要怪的是設計DE2-70的人為什麼非要用nCEO這個pin不可，在pin足夠的的狀況下，應該是不會把nCEO拿來當regular I/O pin來用，除非是在pin不夠用的狀況下，且又只有單顆FPGA時，才會將nCEO也拿來用。在Terasic其他的版子也有類似的設計，熟析了其背後的道理後，也可套用到其他版子上。