移植u-boot-2012.04之建新单板_时钟_SDRAM_UART
(1)新建单板目录,以及配置头文件
tar xjf u-boot-2012.04.01.tar.bz2
cd u-boot-2012.04.01
cd board/samsung/
cp smdk2410 smdk2440 –rf
cd ../..
cd /include/configs/
cp smdk2410.h smdk2440.h
(2) 修改 boards.cfg:
仿照
smdk2410 arm arm920t - samsung s3c24x0
添加:
smdk2440 arm arm920t - samsung s3c24x0
vi命令:
yy:复制当前行到vi缓冲区
p:粘贴缓冲区
、
make smdk2440_config
make
(3) 烧写看结果,没任何输出,并进行调式修改。
更新 source insight工程
(4)分析u-boot启动过程
从start.S开始分析:
阅读代码发现不足:UBOOT里先以60MHZ的时钟计算参数来设置内存控制器,但是MPLL还未设置
处理措施: 把MPLL的设置放到start.S里,取消board_early_init_f里对MPLL的设置
call_board_init_f:
ldrsp, =(CONFIG_SYS_INIT_SP_ADDR)
bicsp, sp, #7 /* 8-byte alignment for ABI compliance */
ldrr0,=0x00000000
blboard_init_f
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {if ((*init_fnc_ptr)() != 0) {hang ();}}
init_fnc_t *init_sequence[] = {#if defined(CONFIG_ARCH_CPU_INIT)arch_cpu_init,/* basic arch cpu dependent setup */#endif#if defined(CONFIG_BOARD_EARLY_INIT_F)board_early_init_f,#endif#ifdef CONFIG_OF_CONTROLfdtdec_check_fdt,#endiftimer_init,/* initialize timer */#ifdef CONFIG_FSL_ESDHCget_clocks,#endifenv_init,/* initialize environment */init_baudrate,/* initialze baudrate settings */serial_init,/* serial communications setup */console_init_f,/* stage 1 init of console */display_banner,/* say that we are here */#if defined(CONFIG_DISPLAY_CPUINFO)print_cpuinfo,/* display cpu info (and speed) */#endif#if defined(CONFIG_DISPLAY_BOARDINFO)checkboard,/* display board info */#endif#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)init_func_i2c,#endifdram_init,/* configure available RAM banks */NULL,};board_early_init_f:
int board_early_init_f(void)修改为:
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */
writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);
/* some delay between MPLL and UPLL */
pll_delay(4000);
/* configure UPLL */
writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);
/* some delay between MPLL and UPLL */
pll_delay(8000);
(5)
编译产生新的uboot,重新运行,观察串口输出
通过openjtag调试uboot,查看到底SDRAM初始化是否正确
显然SDRAM是不对的,接下来 我们自己设置时钟,并修改SDRAM初始化代码。
(6)修改时钟,拷贝测试好的裸机SDRAM内容代码过来用:
去掉:
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldrr0, =CLKDIVN
movr1, #3
strr1, [r0]
改为:
/* 2. 设置时钟 */
ldr r0, =0x4c000014
//mov r1, #0x03; // FCLK:HCLK:PCLK=1:2:4, HDIVN=1,PDIVN=1
mov r1, #0x05; // FCLK:HCLK:PCLK=1:4:8
str r1, [r0]
/* 如果HDIVN非0,CPU的总线模式应该从“fast bus mode”变为“asynchronous bus mode” */
mrcp15, 0, r1, c1, c0, 0/* 读出控制寄存器 */
orrr1, r1, #0xc0000000/* 设置为“asynchronous bus mode” */
mcrp15, 0, r1, c1, c0, 0/* 写入控制寄存器 */
#define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01))
/* MPLLCON = S3C2440_MPLL_200MHZ */
ldr r0, =0x4c000004
ldr r1, =S3C2440_MPLL_400MHZ
str r1, [r0]
/* 启动ICACHE */
mrc p15, 0, r0, c1, c0, 0@ read control reg
orr r0, r0, #(1<<12)
mcrp15, 0, r0, c1, c0, 0 @ write it back
(7)内存不能正常使用,使用以前的配置设置修改:
cpu_init_crit—》lowlevel_init—》
将如下:
SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.word 0x32
.word 0x30
.word 0x30
修改为:
SMRDATA:
.long 0x22011110 //BWSCON
.long 0x00000700 //BANKCON0
.long 0x00000700 //BANKCON1
.long 0x00000700 //BANKCON2
.long 0x00000700 //BANKCON3
.long 0x00000700 //BANKCON4
.long 0x00000700 //BANKCON5
.long 0x00018005 //BANKCON6
.long 0x00018005 //BANKCON7
.long 0x008C04F4 // REFRESH
.long 0x000000B1 //BANKSIZE
.long 0x00000030 //MRSRB6
.long 0x00000030 //MRSRB7
(8)上传新文件,重新make,拷贝执行
到此 ,有乱码输出,串口配置有问题,但经过测试,此时内存已经设置成功。
init_sequence--》serial_init--》
int serial_init(void)serial_init_dev--》_serial_setbrg:
{
return serial_init_dev(UART_NR);
}
reg = get_PCLK() / (16 * gd->baudrate) - 1;
get_PCLK:
ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
#ifdef CONFIG_S3C2440
switch (readl(&clk_power->clkdivn) & 0x6) {
default:
case 0:
return get_FCLK();
case 2:
return get_FCLK() / 2;
case 4:
return (readl(&clk_power->camdivn) & (1 << 9)) ?
get_FCLK() / 8 : get_FCLK() / 4;
case 6:
return (readl(&clk_power->camdivn) & (1 << 8)) ?
get_FCLK() / 6 : get_FCLK() / 3;
}
#else
return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
#endif
}
乱码,查看串口波特率的设置,发现在get_HCLK里没有定义CONFIG_S3C2440
处理措施:include/configs/smdk2440.h: 去掉CONFIG_S3C2410
#define CONFIG_S3C2440
//#define CONFIG_CMD_NAND
(10)更新文件 编译一下,出现如下错误:
(11)重新编译成功
先烧旧的uboot 重启开发板 q –usb下载
注意:此时uboot只支持从nor flash启动
Enter your selection: q
usb 1 30000000
protect off all
erase 0 7ffff
cp.b 30000000 0 80000
重新上电,输出如下,乱码问题解决
U-Boot 2012.04.01 (Apr 18 2017 - 16:17:08)
CPUID: 32440001
FCLK: 400 MHz
HCLK: 100 MHz
PCLK: 50 MHz
DRAM: 64 MiB
WARNING: Caches not enabled
Flash: *** failed ***
### ERROR ### Please RESET the board ###
uboot执行成功:此时 串口、SDRAM、时钟等资源已经初始化成功。uboot正常启动。