Verilog代码编译，但是为什么不运行模拟呢?

My code consists of two files. One file has all the modules and one file has the test bench. When I try to run a simulation on the test bench, I get an unresolved reference error on this line in one of my modules:

我的代码由两个文件组成。一个文件包含所有模块，一个文件有测试工作台。当我尝试在测试台上运行一个模拟时，我在其中一个模块中得到了一个未解决的引用错误:

Add_half (p[3], g[3], in_a[3], in_b[3]);

This line occurs in the module that my test bench calls.

这一行发生在我的测试工作台调用的模块中。

What could be the problem?

有什么问题吗?

This is the code for the test bench. `timescale 1ns/100ps

这是测试工作台的代码。“时间尺度1 ns / 100 ps

module CARRYLOOKAHEAD_TB;

reg [3:0] in_a_tb;
reg [3:0] in_b_tb;
reg in_c0_tb;
wire [3:0] s_tb;
wire c4_tb;

CarryLookAheadAdder DUT (.in_a(in_a_tb), .in_b(in_b_tb), .in_c0(in_c0_tb), .out_s(s_tb), .out_c4(c4_tb));
initial
begin
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b1;
#50 
in_a_tb = 4'b0001;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b1111;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b1111;
in_a_tb = 4'b0000;
in_c0_tb = 1'b1;
#50 $stop;
#20 $finish;
end 
endmodule

This is the code for the module

这是模块的代码。

module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
assign sum = a ^ b; 
assign c_out = a & b; 
endmodule

This is what gets called by the test bench

这就是测试工作台所调用的。

module CarryLookAheadAdder (in_a, in_b, in_c0, out_s, out_c4);
input [3:0] in_a;
input [3:0] in_b;
input in_c0;
output reg [3:0] out_s; 
output reg out_c4;
reg [3:0] p;
reg [3:0] g;
reg [3:0] c;
always@(in_a, in_b, in_c0)
begin
out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0;
Add_half (p[3], g[3], in_a[3], in_b[3]);
Add_half (p[2], g[2], in_a[2], in_b[2]);
Add_half (p[1], g[1], in_a[1], in_b[1]);
Add_half (p[0], g[0], in_a[0], in_b[0]);
out_c4 = c[4];
out_s[3] = p[3] ^ c[3];
out_s[2] = p[2] ^ c[2];
out_s[1] = p[1] ^ c[1];
out_s[0] = p[0] ^ c[0];
end  
endmodule

3 个解决方案

#1

You're missing an instance name. Your simulator probably thinks that statement is a UDP instance so it gives an unresolved reference error during design elaboration. Compilation does not resolve module/UDP instances with definitions so these errors won't cause the compile to fail.

您缺少一个实例名。您的模拟器可能认为该语句是一个UDP实例，因此在设计过程中它给出了一个未解决的引用错误。编译并不能解决带有定义的模块/UDP实例，因此这些错误不会导致编译失败。

Try

试一试

Add_half add_half_inst(p[3], g[3], in_a[3], in_b[3]);

Add_half add_half_inst(p[3],[3],in_a[3],in_b[3]);

EDIT: Add_half is not a function or a task and can't be placed in an always block. It is a module and thus is instanced, not called. Remember you're modeling a logic circuit here.

编辑:Add_half不是一个函数或任务，不能被放置在一个总是块中。它是一个模块，因此是instanced，而不是调用。记住，你在这里建模一个逻辑电路。

Add_half add_half_0(p[3], g[3], in_a[3], in_b[3]);
Add_half add_half_1(p[3], g[3], in_a[3], in_b[3]);
...

Notice each instance has a unique name. You're instancing the same circuit 4 times and simply wiring the inputs and outputs. The instance name is required so they can be uniquely resolved using hierarchical identifiers.

注意每个实例都有一个唯一的名称。你会在相同的电路中运行4次，并简单地连接输入和输出。实例名是必需的，因此可以使用分层标识符来惟一地解决它们。

This won't work as c is [3:0]

这不会像c那样起作用[3:0]

out_c4 = c[4];

Someone might mention a loop but I think you should ignore those for now even though they are appropriate here.

有人可能会提到一个循环，但我认为你现在应该忽略这些，尽管它们在这里是合适的。

#2

In addition to Adam12 & GuanoLoco, just some general notes:

除了Adam12 & GuanoLoco，还有一些一般性的注释:

You are assign out_s[0] twice your CarryLookAheadAdder module

你被分配了两次你的CarryLookAheadAdder模块。

out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0; ... out_s[0] = p[0] ^ c[0];

out_s[0]=(in_a[0]^ in_b[0])^ in_c0;…out_s[0]= p[0]^ c[0];

You aren't using your "g" variable output anywhere. You probably want this to be your "c", as I'm guessing this is your carry.

您没有在任何地方使用“g”变量输出。你可能希望这是你的“c”，因为我猜这是你的随身携带。

#3

In addition to the steps mentioned in Adam12's answer (add instance names, move out of always block), you need to change the type on your connection wires.

除了Adam12的答案中提到的步骤(添加实例名，移出总是块)，还需要在连接连接上更改类型。

reg [3:0] p;
reg [3:0] g;

should be

应该是

wire [3:0] p;
wire [3:0] g;

This is because these are connected directly to the ports on the module. You would only use reg for something that was assigned in the always block.

这是因为它们直接连接到模块上的端口。你只会使用reg，因为它被分配到总是块中。

#1

Try

试一试