module spi_25M(
input clk,
input rst_n,
output reg sdin,
output reg sclk,
output reg cs
);
reg [7:0]cnt;
reg[4:0]state;
reg[15:0]data;
/*
always@(clk)
if(!rst_n)begin sclk<=1; cnt<=0;data=16'b000111_1111_000000;end
else if(cs==0)begin sclk<=!sclk; if(cnt==34)cnt<=0; cnt<=cnt+1;end
*/
always@(posedge clk or negedge rst_n ) begin
if(cs==0)begin sclk<=!sclk; cnt<=cnt+1;end
if(!rst_n)begin cs<=1;sdin<=0;state<=0;cnt<=0;data=16'b000111_1111_000000;sclk<=1;end
else
begin
case(state)
0:if(rst_n==1)begin cs<=0;sdin<=data[15];state<=state+1;end
1:if(cnt==1) begin sdin<=data[14];state<=state+1;end
2:if(cnt==3) begin sdin<=data[13];state<=state+1;end
3:if(cnt==5) begin sdin<=data[12];state<=state+1;end
4:if(cnt==7) begin sdin<=data[11];state<=state+1;end
5:if(cnt==9) begin sdin<=data[10];state<=state+1;end
6:if(cnt==11) begin sdin<=data[9];state<=state+1;end
7:if(cnt==13) begin sdin<=data[8];state<=state+1;end
8:if(cnt==15) begin sdin<=data[7];state<=state+1;end
9:if(cnt==17) begin sdin<=data[6];state<=state+1;end
10:if(cnt==19) begin sdin<=data[5];state<=state+1;end
11:if(cnt==21) begin sdin<=data[4];state<=state+1;end
12:if(cnt==23) begin sdin<=data[3];state<=state+1;end
13:if(cnt==25) begin sdin<=data[2];state<=state+1;end
14:if(cnt==27) begin sdin<=data[1];state<=state+1;end
15:if(cnt==29) begin sdin<=data[0];state<=state+1;end
// 16:if(cnt==31) begin sdin<=data[0];state<=state+1;end
16:if(cnt==31)begin state<=0;cs<=1;cnt<=0;end
endcase
end
end
endmodule