FIQ和IRQ中断系统的区别是什么?

I want to know the difference between FIQ and IRQ interrupt system in any microprocessor, e.g: ARM926EJ.

我想知道FIQ和IRQ中断系统在任何微处理器中的区别。g:ARM926EJ。

11 个解决方案

#1

A feature of modern ARM CPUs (and some others).

现代ARM处理器的一个特点(还有一些其他的)。

From the patent:

从专利:

A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.

提供了一种在具有处理多个中断能力的数字数据处理器中执行快速中断的方法。当收到快速中断请求时，将设置标志，并将程序计数器和条件代码寄存器存储在堆栈中。在中断服务程序结束时，中断指令的返回将检索包含数字数据处理器状态的条件代码寄存器，并检查是否设置了标志。如果设置了标志，则表示服务了一个快速中断，因此只有程序计数器未被堆叠。

In other words, an FIQ is just a higher priority interrupt request, that is prioritized by disabling IRQ and other FIQ handlers during request servicing. Therefore, no other interrupts can occur during the processing of the active FIQ interrupt.

换句话说，FIQ只是一个更高优先级的中断请求，通过在请求服务期间禁用IRQ和其他FIQ处理程序来确定优先级。因此，在活动FIQ中断的处理过程中不会发生其他中断。

#2

ARM calls FIQ the fast interrupt, with the implication that IRQ is normal priority. In any real system, there will be many more sources of interrupts than just two devices and there will therefore be some external hardware interrupt controller which allows masking, prioritization etc. of these multiple sources and which drives the interrupt request lines to the processor.

ARM将FIQ称为快速中断，这意味着IRQ是正常的优先级。在任何真实的系统中，中断的来源都不止两个设备，因此会有一些外部硬件中断控制器，允许对这些多个源进行屏蔽、排序等操作，并将中断请求行驱动到处理器。

To some extent, this makes the distinction between the two interrupt modes redundant and many systems do not use nFIQ at all, or use it in a way analogous to the non-maskable (NMI) interrupt found on other processors (although FIQ is software maskable on most ARM processors).

在某种程度上，这使得这两种中断模式之间的区别变得多余，而且许多系统根本不使用nFIQ，或者以类似于在其他处理器上发现的非可屏蔽(NMI)中断的方式使用nFIQ(尽管FIQ是大多数ARM处理器上可屏蔽的软件)。

So why does ARM call FIQ "fast"?

为什么ARM会叫FIQ“快”?

1. FIQ mode has its own dedicated banked registers, r8-r14. R14 is the link register which holds the return address(+4) from the FIQ. But if your FIQ handler is able to be written such that it only uses r8-r13, it can take advantage of these banked registers in two ways:
   • One is that it does not incur the overhead of pushing and popping any registers that are used by the interrupt service routine (ISR). This can save a significant number of cycles on both entry and exit to the ISR.
   • 其一是，它不会产生推动和取出中断服务例程(ISR)使用的任何寄存器的开销。这可以为ISR的进入和退出节省大量的周期。
   • Also, the handler can rely on values persisting in registers from one call to the next, so that for example r8 may be used as a pointer to a hardware device and the handler can rely on the same value being in r8 the next time it is called.
   • 而且，处理程序可以依赖从一个调用到下一个调用的寄存器中的值，因此，例如，可以将r8用作指向硬件设备的指针，而处理程序可以在下一次调用r8时依赖相同的值。
2. FIQ模式有自己的专用存储寄存器——r8-r14。R14是链接寄存器，它保存FIQ的返回地址(+4)。但是如果你FIQ处理程序能够写,这样它只使用r8-r13,它可以利用这些库存登记在两个方面:一是它不产生推动和弹出任何寄存器的开销由中断服务例程(ISR)使用。这可以为ISR的进入和退出节省大量的周期。而且，处理程序可以依赖从一个调用到下一个调用的寄存器中的值，因此，例如，可以将r8用作指向硬件设备的指针，而处理程序可以在下一次调用r8时依赖相同的值。
3. FIQ location at the end of the exception vector table (0x1C) means that if the FIQ handler code is placed directly at the end of the vector table, no branch is required - the code can execute directly from 0x1C. This saves a few cycles on entry to the ISR.
4. 异常向量表(0x1C)末尾的FIQ位置意味着，如果FIQ处理程序代码直接放在向量表的末尾，则不需要分支——代码可以直接从0x1C执行。这节省了进入ISR的一些周期。
5. FIQ has higher priority than IRQ. This means that when the core takes an FIQ exception, it automatically masks out IRQs. An IRQ cannot interrupt the FIQ handler. The opposite is not true - the IRQ does not mask FIQs and so the FIQ handler (if used) can interrupt the IRQ. Additionally, if both IRQ and FIQ requests occur at the same time, the core will deal with the FIQ first.
6. FIQ的优先级高于IRQ。这意味着，当内核使用FIQ异常时，它会自动屏蔽irq。IRQ不能中断FIQ处理程序。反之则不成立——IRQ不会掩盖FIQ，因此FIQ处理程序(如果使用)可以中断IRQ。此外，如果IRQ和FIQ请求同时发生，核心将首先处理FIQ。

So why do many systems not use FIQ?

那么为什么许多系统不使用FIQ呢?

1. FIQ handler code typically cannot be written in C - it needs to be written directly in assembly language. If you care sufficiently about ISR performance to want to use FIQ, you probably wouldn't want to leave a few cycles on the table by coding in C in any case, but more importantly the C compiler will not produce code that follows the restriction on using only registers r8-r13. Code produced by a C compiler compliant with ARM's ATPCS procedure call standard will instead use registers r0-r3 for scratch values and will not produce the correct cpsr restoring return code at the end of the function.
2. FIQ处理程序代码通常不能用C编写——它需要直接用汇编语言编写。如果您足够关心ISR性能，希望使用FIQ，您可能不希望在任何情况下通过使用C编写代码在表上留下一些循环，但更重要的是，C编译器不会生成仅使用寄存器r8-r13的代码。与ARM的ATPCS过程调用标准兼容的C编译器所生成的代码将会使用寄存器r0-r3来进行初始化，而不会在函数的末尾生成正确的cpsr恢复返回代码。
3. All of the interrupt controller hardware is typically on the IRQ pin. Using FIQ only makes sense if you have a single highest priority interrupt source connected to the nFIQ input and many systems do not have a single permanently highest priority source. There is no value connecting multiple sources to the FIQ and then having software prioritize between them as this removes nearly all the advantages the FIQ has over IRQ.
4. 所有的中断控制器硬件通常都在IRQ引脚上。如果您有一个与nFIQ输入连接的最高优先级中断源，并且许多系统没有一个永久的最高优先级源，那么使用FIQ是有意义的。将多个源连接到FIQ是没有价值的，然后在它们之间设置软件优先级，因为这几乎消除了FIQ相对于IRQ的所有优势。

#3

FIQ or fast interrupt is often referred to as Soft DMA in some ARM references.
Features of the FIQ are,

FIQ或快速中断在某些ARM引用中通常被称为软DMA。FIQ的特点是，

1. Separate mode with banked register including stack, link register and R8-R12.
2. 使用存储寄存器分离模式，包括堆栈、链路寄存器和R8-R12。
3. Separate FIQ enable/disable bit.
4. 单独FIQ启用/禁用。
5. Tail of vector table (which is always in cache and mapped by MMU).
6. 向量表的尾部(它总是在缓存中并由MMU映射)。

The last feature also gives a slight advantage over an IRQ which must branch.

最后一个特性也比必须分支的IRQ略胜一筹。

A speed demo in 'C'

Some have quoted the difficulty of coding in assembler to handle the FIQ. gcc has annotations to code a FIQ handler. Here is an example,

有些人引用了汇编程序中处理FIQ的困难。gcc有注释来编写FIQ处理程序。这是一个例子,

void  __attribute__ ((interrupt ("FIQ"))) fiq_handler(void)
{
    /* registers set previously by FIQ setup. */
    register volatile char *src asm ("r8");  /* A source buffer to transfer. */
    register char *uart asm ("r9");          /* pointer to uart tx register. */
    register int size asm ("r10");           /* Size of buffer remaining. */
    if(size--) {
        *uart = *src++;
    }
}

This translates to the following almost good assembler,

这句话的意思是，

00000000 <fiq_handler>:
   0:   e35a0000        cmp     sl, #0
   4:   e52d3004        push    {r3}            ; use r11, r12, etc as scratch.
   8:   15d83000        ldrbne  r3, [r8]
   c:   15c93000        strbne  r3, [r9]
  10:   e49d3004        pop     {r3}            ; same thing.
  14:   e25ef004        subs    pc, lr, #4

The assembler routine at 0x1c might look like,

0x1c的汇编程序例程可能是这样的，

   tst     r10, #0    ; counter zero?
   ldrbne  r11, [r8]  ; get character.
   subne   r10, #1    ; decrement count
   strbne  r11, [r9]  ; write to uart
   subs    pc, lr, #4 ; return from FIQ.

A real UART probably has a ready bit, but the code to make a high speed soft DMA with the FIQ would only be 10-20 instructions. The main code needs to poll the FIQ r10 to determine when the buffer is finished. Main (non-interrupt code) may transfer and setup the banked FIQ registers by using the msr instruction to switch to FIQ mode and transfer non-banked R0-R7 to the banked R8-R13 registers.

一个真正的UART可能已经准备好了，但是用FIQ来实现高速软DMA的代码只能是10-20条指令。主代码需要轮询FIQ r10以确定缓冲区何时完成。主(非中断代码)可以通过使用msr指令切换到FIQ模式并将非banked R0-R7转换为banked R8-R13寄存器，从而传输和设置banked FIQ寄存器。

Typically RTOS interrupt latency will be 500-1000 instructions. For Linux, it maybe 2000-10000 instructions. Real DMA is always preferable, however, for high frequency simple interrupts (like a buffer transfer), the FIQ can provide a solution.

RTOS中断延迟通常为500-1000条指令。对于Linux，它可能是2000-10000个指令。真正的DMA总是更好的，但是，对于高频简单中断(如缓冲区传输)，FIQ可以提供一个解决方案。

As the FIQ is about speed, you shouldn't consider it if you aren't secure in coding in assembler (or willing to dedicate the time). Assembler written by an infinitely running programmer will be faster than a compiler. Having GCC assist can help a novice.

由于FIQ是关于速度的，所以如果您在汇编程序中编码不安全(或者愿意花时间)，您不应该考虑它。由无限运行的程序员编写的汇编程序将比编译程序快。有GCC的帮助可以帮助新手。

Latency

As the FIQ has a separate mask bit it is almost ubiquitously enabled. On earlier ARM CPUs (such as the ARM926EJ), some atomic operations had to be implemented by masking interrupts. Still even with the most advanced Cortex CPUs, there are occasions where an OS will mask interrupts. Often the service time is not critical for an interrupt, but the time between signalling and servicing. Here, the FIQ also has an advantage.

由于FIQ有一个单独的掩码位，所以它几乎是普遍启用的。在早期的ARM cpu(如ARM926EJ)上，一些原子操作必须通过屏蔽中断来实现。即使是最先进的皮质cpu，有时也会出现操作系统屏蔽中断的情况。通常，服务时间对中断不是很关键，而是信号和服务之间的时间。在这里，FIQ也有一个优势。

Weakness

The FIQ is not scalable. In order to use multiple FIQ sources, the banked registers must be shared among interrupt routines. Also, code must be added to determine what caused the interrupt/FIQ. The FIQ is generally a one trick pony.

FIQ是不可扩展的。为了使用多个FIQ源，在中断例程中必须共享banked寄存器。另外，必须添加代码以确定是什么导致了中断/FIQ。FIQ通常是一个诡计多端的小马。

If your interrupt is highly complex (network driver, USB, etc), then the FIQ probably makes little sense. This is basically the same statement as multiplexing the interrupts. The banked registers give 6 free variables to use which never load from memory. Register are faster than memory. Registers are faster than L2-cache. Registers are faster than L1-cache. Registers are fast. If you can not write a routine that runs with 6 variables, then the FIQ is not suitable. Note: You can double duty some register with shifts and rotates which are free on the ARM, if you use 16 bit values.

如果您的中断非常复杂(网络驱动程序、USB等)，那么FIQ可能没有什么意义。这基本上与对中断进行多路复用是相同的。存储寄存器提供了6个*变量供使用，它们从不从内存中加载。寄存器比内存快。寄存器比l2缓存快。寄存器比l1缓存快。寄存器是快。如果您不能编写一个带有6个变量的例程，那么FIQ是不合适的。注意:如果您使用16位值，您可以使用在手臂上免费的一些移位寄存器和旋转寄存器。

Obviously the FIQ is more complex. OS developers want to support multiple interrupt sources. Customer requirements for a FIQ will vary and often they realize they should just let the customer roll their own. Usually support for a FIQ is limited as any support is likely to detract from the main benefit, SPEED.

显然FIQ更复杂。OS开发人员希望支持多个中断源。FIQ的客户需求会有所不同，通常他们会意识到他们应该让客户自己来做。通常对FIQ的支持是有限的，因为任何支持都可能会减少主要的好处，速度。

Summary

Don't bash my friend the FIQ. It is a system programers one trick against stupid hardware. It is not for everyone, but it has its place. When all other attempts to reduce latency and increase ISR service frequency has failed, the FIQ can be your only choice (or a better hardware team).

不要抨击我的朋友。这是一个系统程序员对付愚蠢硬件的一个技巧。它并不适合所有人，但它有自己的位置。当所有其他降低延迟和增加ISR服务频率的尝试都失败时，FIQ可以是您的唯一选择(或者更好的硬件团队)。

It also possible to use as a panic interrupt in some safety critical applications.

在某些安全关键应用程序中，也可以将其用作紧急中断。

#4

Chaos has already answered well, but an additional point not covered so far is that FIQ is at the end of the vector table and so it's common/traditional to just start the routine right there, whereas the IRQ vector is usually just that. (ie a jump to somewhere else). Avoiding that extra branch immediately after a full stash and context switch is a slight speed gain.

混沌已经回答得很好了，但是到目前为止还没有提到的一点是FIQ在向量表的末尾，所以通常/传统的做法是在这里开始例程，而IRQ向量通常就是这样。(跳转到别的地方)。在完全隐藏和上下文切换之后立即避免额外的分支是一个微小的速度增益。

#5

FIQ is higher priority, and can be introduced while another IRQ is being handled. The most critical resource(s) are handled by FIQ's, the rest are handled by IRQ's.

FIQ是更高的优先级，可以在处理另一个IRQ时引入。最关键的资源由FIQ处理，其余的由IRQ处理。

#6

another reason is in case of FIQ, lesser number of register is needed to push in the stack, FIQ mode has R8 to R14_fiq registers

另一个原因是在FIQ的情况下，在栈中推入寄存器的数量较少，FIQ模式有R8到R14_fiq寄存器

#7

I believe this is what you are looking for:

我相信这就是你想要的:

http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.arm/2005-09/msg00084.html

http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.arm/2005-09/msg00084.html

Essentially, FIQ will be of the highest priority with multiple, lower priority IRQ sources.

从本质上讲，FIQ将是具有多个优先级较低的IRQ源的最高优先级。

#8

No any magic about FIQ. FIQ just can interrupt any other IRQ which is being served,this is why it is called 'fast'. The system reacts faster on these interrupts but the rest is the same.

FIQ没有任何魔力。FIQ可以中断任何其他正在服务的IRQ，这就是为什么它被称为“fast”。系统对这些中断反应更快，但其余的都是一样的。

#9

FIQs are higher priority, no doubt, remaining points i am not sure..... FIQs will support high speed data transfer (or) channel processing, where high speed data processes is required we use FIQs and generally IRQs are used normal interrupt handlling.

FIQs是更高的优先级，毫无疑问，剩下的点我不确定……FIQs将支持高速数据传输(或)通道处理，在需要高速数据处理的地方，我们使用FIQs，通常IRQs是使用普通中断处理。

#10

It Depends how we design interrupt handlers, as FIQ is at last it may not need one branch instruction, also it has unique set of r8-r14 registers so next time we come back to FIQ interrupt we do not need to push/pop up the stack. Ofcourse it saves some cycles, but again it is not wise to have more handlers serving one FIQ and yes FIQ is having more priority but it is not any reason to say it handles the interrupt faster, both IRQ/FIQ run at same CPU frequency, So they must be running at same speed.

这取决于我们如何设计中断处理程序，因为FIQ最后可能不需要一个分支指令，它也有独特的r8-r14寄存器组，所以下次我们回到FIQ中断时，我们不需要push/弹出堆栈。当然它节省了一些周期,但是它不是明智的有更多的处理程序提供一个FIQ是的FIQ有更多优先但没有任何理由说它处理中断更快,IRQ / FIQ运行在相同的CPU频率,所以他们必须以相同的速度运行。

#11

This may be wrong. All I know is that FIQ stands for Fast Interrupt Request and that IRQ stands for Interrupt Request. Judging from these names, I will guess that a FIQ will be handled(thrown?) faster than an IRQ. It probably has something to do with the design of the processor where an FIQ will interrupt the process faster than an IRQ. I apologize if I'm wrong, but I normally do higher level programming, I'm just guessing right now.

这可能是错误的。我只知道FIQ代表快速中断请求，IRQ代表中断请求。从这些名字来看，我猜FIQ会比IRQ处理得更快。它可能与处理器的设计有关，FIQ会比IRQ更快地中断进程。如果我说错了，我很抱歉，但我通常会做更高层次的编程，我现在只是在猜测。