在系统verilog中打包vs unpacked向量

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:

看一下我在System Verilog中维护的一些代码,我看到一些定义如下的信号:

node [range_hi:range_lo]x;

and others that are defined like this:

和其他定义如下:

node y[range_hi:range_lo];

I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.

我知道x被定义为packed,而y被定义为unpacked。但是,我不知道这意味着什么。

What is the difference between packed and unpacked vectors in System Verilog?

System Verilog中的打包和解包矢量有什么区别?

Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?

编辑:回应@Empi的答案,为什么要在SV中编写的硬件设计师关心数组的内部表示?有没有时候我不应该或不能使用打包信号?

5 个解决方案

#1

This article gives more details about this issue: http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

本文提供了有关此问题的更多详细信息:http://electrosofts.com/systemverilog/arrays.html,尤其是第5.2节。

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

打包数组是一种将矢量细分为子字段的机制,可以方便地将其作为数组元素进行访问。因此,保证打包数组被表示为连续的位组。解包的阵列可能会也可能不会如此表示。打包数组与解压缩数组的不同之处在于,当打包数组作为主数组出现时,它被视为单个向量。

#2

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration. Packed arrays have an object name comes before size declaration. For example:

在了解完全打包和解包的数组之前,还可以看看如何通过声明来了解哪个数组是什么。打包数组在大小声明之前有一个对象名称。例如:

bit [3][7] a;

Unpacked array have an object name comes after size declaration. For example:

解包后的数组在大小声明后有一个对象名称。例如:

bit a[3];

Packed array make memory whereas Unpacked dont. You can access/declare unpacked array like this also

打包的数组使内存,而解压缩不。您也可以像这样访问/声明解压缩的数组

reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1};

You can mix both packed and unpacked array to make a multidimensional memory. For example:

您可以混合打包和解压缩的数组来创建多维内存。例如:

bit [3:0][7:0]a[2:0].

It makes an array of 4 (i.e. 4*8) bytes with depth of 3.

它产生一个4(即4 * 8)字节的数组,深度为3。

#3

Packed array are mainly used for effective memory usage when we are writing a [3:0][7:0]A[4:0] which means in 32 bit memory locations 4slices each of 8 bit are packed to form a 32 bit. The right side value means there are 5 such slices are there.

当我们写入[3:0] [7:0] A [4:0]时,打包数组主要用于有效的内存使用,这意味着在32位存储器位置中,每个8位的4个数据被打包形成32位。右侧值意味着有5个这样的切片。

#4

Unpacked arrays will give you more compile time error checking than packed arrays.

解压缩的数组将比打包的数组提供更多的编译时错误检查。

I see unpacked arrays on the port definitions of modules for this reason. The compiler will error if the dimensions of the signal are not exactly the same as the port with unpacked arrays. With packed arrays it will normally just go ahead and wire things the best it can, not issuing an error.

出于这个原因,我在模块的端口定义上看到了解压缩的数组。如果信号的尺寸与具有解压缩阵列的端口不完全相同,编译器将会出错。对于打包数组,它通常会继续并尽可能地连接事物,而不是发出错误。

#5

bit[3:0] a -> packed array The packed array can be used as a full array (a='d1) or just part of an array (a[0]='b1)

bit [3:0] a - >压缩数组压缩数组可以用作完整数组(a ='d1)或只是数组的一部分(a [0] ='b1)

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

bit a [3:0] - > unpacked array解包后的数组不能用作[0] ='b1,必须用作完全a = {8 {'b1}}

#1