系统verilog绑定与接口一起使用。

I defined an interface in system verilog and use bind statement to bind to internal RTL signals. I want to be able to force internal RTL signals through the interface. However, this is causing the RTL signal to go to 'x' if I don't force these signals explicitly, it seems bind to interface is having driving capability. I don't want RTL signal to change to 'x' when nothing is forcing it in this case, not sure what I am doing wrong here?

我在系统verilog中定义了一个接口，并使用bind语句绑定到内部RTL信号。我希望能够通过接口强制内部RTL信号。然而，这导致RTL信号进入“x”，如果我不明确强制这些信号，它似乎绑定到接口具有驱动能力。我不希望RTL信号改变为x当没有任何东西强迫它在这个情况下，不确定我在这里做错了什么?

my code looks like this with DUT being the design:

我的代码是这样的，DUT是设计:

interface myInf(
   inout RTL_a,
   inout RTL_b 
);

bind DUT myInf myInf_inst(
   .RTL_a(DUT.a),
   .RTL_b(DUT.b)
);

bind DUT myDrv(myInf_inst);

where myDrv is a module which drives the ports on myInf.

myDrv是在myInf上驱动端口的模块。

In this case, DUT.a and DUT.b are internal RTL signals, they have their driver from design, but I want to be able to force them if needed. however, these signals becoming 'x' when I am just binding them to myInf without actually driving them.

在这种情况下,DUT。和灰尘。b是内部RTL信号，他们有来自设计的驱动，但是我想在需要的时候能够强迫他们。然而，当我将它们绑定到myInf时，这些信号就变成了“x”，而实际上并没有驱动它们。

1 个解决方案

#1

The inout signals might be a non-net type. It is better to be explicit in the the declaration and define them as inout wire. Inside the interface, assign the nets to a logic and initialize the logics to z. A non-z value will apply a driver while a z will allow signals to drive. Example:

inout信号可能是一个非网络类型。最好在声明中显式，并将其定义为inout wire。在接口内部，将网络分配给一个逻辑，并将逻辑初始化为z。一个非z值将应用一个驱动程序，而z将允许信号驱动。例子:

interface myInf(
   inout wire RTL_a,
   inout wire RTL_b 
);
  logic drv_a, drv_b;
  initial {drv_a,drv_b} = 'z; // z means not driving
  assign RTL_a = drv_a;
  assign RTL_b = drv_b;
endinterface

There might be conflicting drivers, such as the normal drivers from the design. In this case you will need to override the driver. Assuming the signal being overrode is a net type, this is done by changing the assign statements to assign (supply1,suppl0) RTL_a = drv_a;. This is utilizing the Verilog concept of drive strength. Assigning to z will still all other drivers. Most nets are driven with a strength of strong1,strong0 which is weaker then supply1,supply0. Drive strength will not work for non-net types (e.g. logic & reg). These register/variable-types use a last-assignment-wins approach. Fore more on drive strength read IEEE Std 1800-2012 sections 28.11 through 28.15

可能会有冲突的驱动程序，比如来自设计的普通驱动程序。在这种情况下，您需要重写驱动程序。假设被覆盖的信号是一个网络类型，这是通过改变分配语句来分配的(补充，补充)RTL_a = drv_a;这是利用了驱动强度的Verilog概念。分配给z仍然是所有其他驱动程序。大多数网的驱动力是强，强，强，弱，然后供给，供给。驱动强度不适用于非网络类型(如逻辑和reg)。这些寄存器/变量类型使用最后的赋值方法。更多的关于驱动强度阅读IEEE Std 1800-2012章节28.11到28.15。

Your sample code has some bugs. The pin connections for myInf_inst should use hierarchical references relative to its target scope. Unless there is an instance called DUT inside module DUT, then the DUT. should be omitted (See IEEE Std 1800-2012 § 23.11 Binding auxiliary code to scopes or instances). The bind statement for myDrv is missing an instance name. The code should be:

您的样例代码有一些错误。myInf_inst的pin连接应该使用相对于其目标范围的层次引用。除非有一个叫做DUT的实例在模块DUT中，然后是DUT。应该省略(见1800 - 2012年IEEE Std§23.11绑定辅助代码范围或实例)。myDrv的绑定语句缺少一个实例名。代码应该是:

bind DUT myInf myInf_inst(
   .RTL_a(a), // no DUT.
   .RTL_b(b) // no DUT.
);

bind DUT myDrv myDrv_inst(myInf_inst);

sample code: http://www.edaplayground.com/x/2NG

示例代码:http://www.edaplayground.com/x/2NG

#1

interface myInf(
   inout wire RTL_a,
   inout wire RTL_b 
);
  logic drv_a, drv_b;
  initial {drv_a,drv_b} = 'z; // z means not driving
  assign RTL_a = drv_a;
  assign RTL_b = drv_b;
endinterface

bind DUT myInf myInf_inst(
   .RTL_a(a), // no DUT.
   .RTL_b(b) // no DUT.
);

bind DUT myDrv myDrv_inst(myInf_inst);

sample code: http://www.edaplayground.com/x/2NG

示例代码:http://www.edaplayground.com/x/2NG

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系统verilog绑定与接口一起使用。

1 个解决方案

#1

#1

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