本文源自：https://pdos.csail.mit.edu/6.828/2014/readings/i386/c05.htm#fig5-1 (Intel 80386 Reference Programmer's Manual)
首先是逻辑地址，线性地址，物理地址间的区别与联系，可以见下图（图中虚拟地址即指逻辑地址）：
注意上图中的分页机制有问题，需将 PAGING ENABLED 与 PAGING DISABLED 的文字位置相互交换。
1 Segment Translation
To perform this translation, the processor uses the following data structures:1)Descriptors
2)Descriptor tables
3)Selectors
4)Segment Registers
1.1 Descriptors
The segment descriptor provides the processor with the data it needs to map a logical address into a linear address. Descriptors are created by compilers, linkers, loaders, or the operating system, not by applications programmers.
two general descriptor formats:
1.2 Descriptor Tables
描述符表分为 GDT 和 LDT 两种。
A descriptor table is simply a memory array of 8-byte(64-bit) entries that contain descriptors, as Figure 5-5 shows.
1.3 Selectors
The selector portion of a logical address identifies a descriptor by specifying a descriptor table and indexing a descriptor within that table. Selectors may be visible to applications programs as a field within a pointer variable, but the values of selectors are usually assigned (fixed up) by linkers or linking loaders.
Index: Selects one of 8192(2^13) descriptors in a descriptor table.The processor simply multiplies this index value by 8 (the length of a descriptor), and adds the result to the base address of the descriptor table(此处我感觉应该是GDTR) in order to access the appropriate segment descriptor in the table.
当T = 0 时，也即选择的是 GDT，当 T = 1 时，选择的是LDT。
GDTR中存放的是GDT在内存中的基地址和其表长界限。
1.4 Segment Registers
The 80386 stores information from descriptors in segment registers, thereby avoiding the need to consult a descriptor table every time it accesses memory.The visible portions of these segment address registers are manipulated by programs as if they were simply 16-bit registers. The invisible portions are manipulated by the processor.
完整的逻辑地址转线性地址过程图如下：
2 Page Translation
The page-translation step is optional. Page translation is in effect only when the PG bit of CR0 is set. This bit is typically set by the operating system during software initialization. The PG bit must be set if the operating system is to implement multiple virtual 8086 tasks, page-oriented protection, or page-oriented virtual memory.
2.1 Page Frame
A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin onbyte boundaries and are fixed in size.
2.2 Linear Address
A linear address refers indirectly to a physical address by specifying a page table, a page within that table, and an offset within that page.
2.3 Page Tables
A page table is simply an array of 32-bit page specifiers. A page table is itself a page, and therefore contains 4 Kilobytes of memory or at most 1K 32-bit entries.
Two levels of tables are used to address a page of memory. At the higher level is a page directory. The page directory addresses up to 1K page tables of the second level. A page table of the second level addresses up to 1K pages. All the tables addressed by one page directory, therefore, can address 1M pages (2^(20)). Because each page contains 4K bytes 2^(12) bytes), the tables of one page directory can span the entire physical address space of the 80386 (2^(20) times 2^(12) = 2^(32)).
2.4 Page-Table Entries
2.4.1 Page Frame Address
The page frame address specifies the physical starting address of a page.(注意是物理地址) Because pages are located on 4K boundaries, the low-order 12 bits are always zero. In a page directory, the page frame address is the address of a page table. In a second-level page table, the page frame address is the address of the page frame that contains the desired memory operand.
2.4.２Present Bit
The Present bit indicates whether a page table entry can be used in address translation. P=1 indicates that the entry can be used.When P=0 in either level of page tables, the entry is not valid for address translation, and the rest of the entry is available for software use; none of the other bits in the entry is tested by the hardware.
2.4.3 Accessed and Dirty Bits
These bits provide data about page usage in both levels of the page tables. With the exception of the dirty bit in a page directory entry, these bits are set by the hardware; however, the processor does not clear any of these bits.
The processor sets the corresponding accessed bits in both levels of page tables to one before a read or write operation to a page.
The processor sets the dirty bit in the second-level page table to one before a write to an address covered by that page table entry. The dirty bit in directory entries is undefined.
The processor sets the dirty bit in the second-level page table to one before a write to an address covered by that page table entry. The dirty bit in directory entries is undefined.
An operating system that supports paged virtual memory can use these bits to determine what pages to eliminate from physical memory when the demand for memory exceeds the physical memory available. The operating system is responsible for testing and clearing these bits.
2.4.4 Read/Write and User/Supervisor Bits
These bits are not used for address translation, but are used for page-level protection, which the processor performs at the same time as address translation . Refer to Chapter 6 where protection is discussed in detail.
2.5 Page Translation Cache
For greatest efficiency in address translation, the processor stores the most recently used page-table data in an on-chip cache. Only if the necessary paging information is not in the cache must both levels of page tables be referenced.
3 Combining Segment and Page Translation
3.1 "Flat" Architecture
When the 80386 is used to execute software designed for architectures that don't have segments, it may be expedient to effectively "turn off" the segmentation features of the 80386. The 80386 does not have a mode that disables segmentation, but the same effect can be achieved by initially loading the segment registers with selectors for descriptors that encompass the entire 32-bit linear address space. Once loaded, the segment registers don't need to be changed. The 32-bit offsets used by 80386 instructions are adequate to address the entire linear-address space.
3.2 Segments Spanning Several Pages
The architecture of the 80386 permits segments to be larger or smaller than the size of a page (4 Kilobytes). For example, suppose a segment is used to address and protect a large data structure that spans 132 Kilobytes. In a software system that supports paged virtual memory, it is not necessary for the entire structure to be in physical memory at once. The structure is divided into 33 pages, any number of which may not be present. The applications programmer does not need to be aware that the virtual memory subsystem is paging the structure in this manner.
3.3 Pages Spanning Several Segments
On the other hand, segments may be smaller than the size of a page. For example, consider a small data structure such as a semaphore. Because of the protection and sharing provided by segments , it may be useful to create a separate segment for each semaphore. But, because a system may need many semaphores, it is not efficient to allocate a page for each. Therefore, it may be useful to cluster many related segments within a page.
3.4 Non-Aligned Page and Segment Boundaries
The architecture of the 80386 does not enforce any correspondence between the boundaries of pages and segments. It is perfectly permissible for a page to contain the end of one segment and the beginning of another. Likewise, a segment may contain the end of one page and the beginning of another.
3.5 Aligned Page and Segment Boundaries
Memory-management software may be simpler, however, if it enforces some correspondence between page and segment boundaries. For example, if segments are allocated only in units of one page, the logic for segment and page allocation can be combined. There is no need for logic to account for partially used pages.
3.6 Page-Table per Segment
An approach to space management that provides even further simplification of space-management software is to maintain a one-to-one correspondence between segment descriptors and page-directory entries, as Figure 5-13 illustrates. Each descriptor has a base address in which the low-order 22 bits are zero; in other words, the base address is mapped by the first entry of a page table. A segment may have any limit from 1 to 4 megabytes. Depending on the limit, the segment is contained in from 1 to 1K page frames. A task is thus limited to 1K segments (a sufficient number for many applications), each containing up to 4 Mbytes. The descriptor, the corresponding page-directory entry, and the corresponding page table can be allocated and deallocated simultaneously.
