CIC 抽取滤波器 Verilog Code

时间：2022-03-10 10:17:00

采用流水线结构的CIC 抽取滤波器结构如下：
// 三级CIC抽取器实例：cic3_decimator.V
module cic3_decimator(clk, x_in, y_out);
parameter STATE_HOLD = 1'b0, STATE_SAMPLE = 1'b1;
input clk; // 输入时钟
input [7:0] x_in; // 输入8位数据
output [25:0] y_out; // 输出26位数据
reg state, derived_clk;
reg [4:0] counter;
// 有限状态机，用于实现下采样
always @(negedge clk) begin: FSM_DECIMATOR
case(state)
STATE_HOLD: begin
if(counter == 31)
state <= STATE_SAMPLE;
end
STATE_SAMPLE: begin
ComReg0[0] <= IntReg[2];
state <= STATE_HOLD;
end
default:
state <= STATE_HOLD;
endcase
if((counter>8)&&(counter<16)) // 生成下采样后的时钟
derived_clk <= 1;
else
derived_clk <= 0;
counter <= counter + 1;
end
wire [25:0] sxtx; // Sign extended input
assign sxtx = {{18{x[7]}},x}; // 符号扩展
reg [7:0] x; // Registered input
reg [25:0] IntReg[2:0]; // I section 0,1 and 2
// 积分器实现模块
always @(posedge clk) begin: INTEGRATOR
x <= x_in;
IntReg[0] <= IntReg[0] + sxtx;
IntReg[1] <= IntReg[1] + IntReg[0];
IntReg[2] <= IntReg[2] + IntReg[1];
end
reg [25:0] ComReg0[2:0],ComReg1[2:0],ComReg2[2:0],ComReg3;
//梳状器实现模块
always @(posedge derived_clk)begin:COMB
ComReg0[1] <= ComReg0[0];
ComReg0[2] <= ComReg0[1];
ComReg1[0] <= ComReg0[0] - ComReg0[2];
ComReg1[1] <= ComReg1[0];
ComReg1[2] <= ComReg1[1];
ComReg2[0] <= ComReg1[0] - ComReg1[2];
ComReg2[1] <= ComReg2[0];
ComReg2[2] <= ComReg2[1];
ComReg3 <= ComReg2[0] - ComReg2[2];
end
assign y_out = ComReg3; //输出
endmodule

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CIC 抽取滤波器 Verilog Code

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