深入分析GPIOPS驱动代码 – 2， Zedboard ，Zynq-7000

GpioPs in Depth 2

We are trying to use the gpio in varying kinds of way, such as routing the gpio module to emio port, in order to use the ld0-ld7 and sw0-sw7 on zedboard.

1. Start Xilinx PlanAhead and build a embedded source named system, double click to edit in Xilinx XPS. Refer to the previous blog for details.
2. We just route the gpiops module to emio port, without any use of pl logic,so configure the xps as follows:
   1. Click the I/O Periphals, Zynq PS MIO Configuration Box appears, extract the GPIO item in left panel and enable the EMIO GPIO item by click on it. Type 16 in the following input window, which means we are planning to use 16 pins of gio module and route it via emio.

   

   1. In System Assembly View , Click the Ports tablet and we will route the signal : (IO_IF)GPIO_0 to external pin. Set it as follows:

   

   1. Project>Design Rule Check, if no error occurs, exit Xilinx XPS and turn back PlanAhead.
   2. Right Click on System(System.xml) and select Create TOP HDL.
   3. Click Run Synthesis on the Flow Navigator panel.
   4. After a exhausting time, it ends. Select Open Syntheized Design and ignore the warning dialog window.
   5. Select Window>I/O Ports, in the I/O Ports tablet , configure the signals to fixed chip pins, as shown :

      

      NOTICE:

      

      The above dialog appears once you assign the same pin on different signals.

      Points:

      We can see the column Bank in the I/O Ports table and it's different from the GPIOPS bank definition:

      GPIOPS BANK Definition:    BANK0/1 --> MIO

                              BANK2/3 --> EMIO

      Bank Voltage Definition:

      

      Refers to Zedboard_HW_UG.pdf for more details.

       

You can edit the GpioPs.ucf by double click on it and edit as follows:

NET "processing_system7_0_GPIO_pin[0]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[1]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[2]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[3]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[15]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[14]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[13]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[12]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[11]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[10]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[9]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[8]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[7]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[6]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[5]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[4]" IOSTANDARD = LVCMOS25;

NET "processing_system7_0_GPIO_pin[0]" LOC = T22;

NET "processing_system7_0_GPIO_pin[1]" LOC = T21;

NET "processing_system7_0_GPIO_pin[2]" LOC = U22;

NET "processing_system7_0_GPIO_pin[3]" LOC = U21;

NET "processing_system7_0_GPIO_pin[4]" LOC = V22;

NET "processing_system7_0_GPIO_pin[5]" LOC = W22;

NET "processing_system7_0_GPIO_pin[6]" LOC = U19;

NET "processing_system7_0_GPIO_pin[7]" LOC = U14;

NET "processing_system7_0_GPIO_pin[8]" LOC = F22;

NET "processing_system7_0_GPIO_pin[9]" LOC = G22;

NET "processing_system7_0_GPIO_pin[10]" LOC = H22;

NET "processing_system7_0_GPIO_pin[11]" LOC = F21;

NET "processing_system7_0_GPIO_pin[12]" LOC = H19;

NET "processing_system7_0_GPIO_pin[13]" LOC = H18;

NET "processing_system7_0_GPIO_pin[14]" LOC = H17;

NET "processing_system7_0_GPIO_pin[15]" LOC = M15;

DO NOT forget the 'NET" Key word and remember to save the ucf file use "CTRL+S" short key.

1. Select File>Export>Export Hardware for SDK, select Launch SDK item and click OK, turn to SDK application.

POINTS:

Once your PlanAhead stuck loop endlessly, recommend you use the 32bit version of PlanAhead, and it seems stable.

 

1. Select File>New>Application Project, type project name: GpioPsinDepth and select finish, the wizard completed with a helloworld.c created.
2. Double click on helloworld.c to edit it, include "XGpioPs.h", and type main function as follows:

XGpioPs_Config* pGpioPsCfg;

XGpioPs GpioPs;

pGpioPsCfg=XGpioPs_LookupConfig(XPAR_XGPIOPS_0_DEVICE_ID);

XGpioPs_CfgInitialize(&GpioPs,pGpioPsCfg,pGpioPsCfg->BaseAddr);

XGpioPs_SetDirection(&GpioPs,XGPIOPS_BANK2,0xFF);

XGpioPs_SetOutputEnable(&GpioPs,XGPIOPS_BANK2,0xFF);

XGpioPs_Write(&GpioPs,XGPIOPS_BANK2,0xFF);

 

while(1)

{

 

    u32 Data;

    Data=XGpioPs_Read(&GpioPs,XGPIOPS_BANK2);

    Data&=(0xFF00);

    Data>>=8;

    XGpioPs_Write(&GpioPs,XGPIOPS_BANK2,Data);

 

}

 

1. (ISE 14.5 only, for 14.4 just go to step 6)Select Xilinx Tools>Launch Hardware Server.

 

1. Right Click on GpioPsinDepth Project , Select Run as>Run Configuration, right click on Xilinx C/C++ ELF and choose New to create a new target, and enable Connect STDIO to Console in SDIO Connection on the right side. Click run to download into chip.

 

1. What a surprise! Just Change each Switch(SW0-SW7) and the LD0-LD7 make the same changes.

 

1. Thanks.

 

Problems issued:

    In Xilinx ISE 14.4, you need to click on the I/O peripherals block to enable GPIO on EMIO Interface, Instead of clicking the 32b GP AXI Master Ports to enable GPIO on EMIO Interface.

    Be Noticed that once you enable the gpio emio pin number, go directly to the Ports table and configure the extern pin of (IO_IF)GPIO_0. You maybe find the Enable GPIO on EMIO Interface disabled again once you click the 32b GP AXI Master Ports to verify the setting.