测试驱动开发，测试先行。
matlab可以很方便的为modlesim生成仿真数据，也可以非常方便的观察仿真的结果。
一、用matlab生成数据源的方法：
len=1024;
fs=50000000;
fc=1000000;
dfi=2*pi*fc/fs;
sig=sin((1:1:len)*dfi);
sig=int16(sig*1000);
fid=fopen('sigin.txt','wt');
fprintf(fid,'%d\n',sig);
fclose(fid);
二、在modelsim读取仿真数据以及输出仿真结果
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio;
use std.textio.all;
entity tb_datainout is
constant INPUT_FILE : string := "sigin.txt";
constant OUTPUT_FILE : string :="sigout.txt";
constant DATA_WIDTH : natural := 16;
end entity tb_datainout;
architecture rtl of tb_datainout is
signal data_inout : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0');
signal clk : std_logic := '0';
constant tclk : time := 10 ns;
begin
clkgen : process
begin -- process clkgen
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end process clkgen;
inoutmodel : process(clk) is
file in_file : text open read_mode is INPUT_FILE;
file out_file : text open write_mode is OUTPUT_FILE;
variable data_in : integer;
variable indata : line;
variable outdata : line;
variable data_out:integer;
begin
if rising_edge(clk) then
if not endfile(in_file) then
readline(in_file, indata);
read(indata, data_in);
data_inout <= std_logic_vector(to_signed(data_in, DATA_WIDTH)) after tclk/4;
else
data_inout <= data_inout after tclk/4;
end if;
data_out:= to_integer(signed(data_inout));
write(outdata, data_out);
writeline(out_file, outdata);
end if;
end process inoutmodel;
end architecture rtl;