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文件名称:How to Efficiently Analyze a DDR4 Interface
文件大小:3.65MB
文件格式:PDF
更新时间:2022-09-02 06:45:08
cadence ddr4 signalintegrity 信号完整性分析
DDR4接口分析,2015年Cadence课程分享ppt。目录如下:
• Power-aware signal integrity (SI) in memory bus design and analysis
• Modeling methodology for integrated core and power-aware parallel bus system with Cadence-Sigrity tools
• Building an integrated core and power-aware parallel bus system in Cadence-Sigrity tool environment
• Case study
– A virtual reference design based on the Cadence DDR4 IP test chip, package, and PCB
– Simulation and measurement correlation