【文件属性】：
文件名称：FPGA常见警告与FPGA错误集锦
文件大小：71KB
文件格式：DOC
更新时间：2017-05-12 12:33:11
FPGA常见警告 FPGA错误集锦
1.Found clock-sensitive change during active clock edge at time
on register ""
2.Verilog HDL assignment warning at : truncated value with size to match size of target (
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Found pins functioning as undefined clocks and/or memory enables
.Timing characteristics of device EPM570T144C5 are preliminary
Design contains input pin(s) that do not drive logic
Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
