Bringing Agile Methods Into Functional Verification

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文件名称：Bringing Agile Methods Into Functional Verification
文件大小：498KB
文件格式：PDF
更新时间：2013-01-03 07:31:49
Bringing Agile Methods Into Functional Agile Programming is a highly disciplined methodology used in software engineering. One aspect of the Agile methodology that is applicable to ASIC/FPGA functional verification and particularly important when creating verification environments using an Object Oriented paradigm is the Test Driven Development [2]. This process encourages the creation of a separate unit test for every critical class that is defined in a system. This paper describes the value of using a SystemVerilog unit test framework when creating a functional verification environment. Applying this Agile aspect may help achieve improvements in both quality and productivity. The usage model, the design of a unit test framework created for SystemVerilog (called svunit), and a concrete example of its usage are also presented.