VHDL第一次用，不知道怎么改错误，求大神指点

Error (10500): VHDL syntax error at Vhdl2.vhd(17) near text "";  expecting "then"
Error (10500): VHDL syntax error at Vhdl2.vhd(17) near text
Error (10500): VHDL syntax error at Vhdl2.vhd(23) near text "if";  expecting "process"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 531 megabytes
Error: Processing ended: Sat Dec 24 20:33:29 2016
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 0 warnings

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ppt is
port(clk     : in std_logic;
      start  : in std_logic;
      x      : in std_logic;
      y      : out std_logic);
end ppt;
architecture behav of askt is
signal q:integer range 0 to 3;
signal f:std_logic;
begin
process(clk)
begin
if clk'event and clk=’1’then
     if start='0' then q<=0;
     elsif q<=1 then f<='1';q<=q+1;
     elsif q=3 then f<='0';q<=0;
     else f<='0';q<=q+1;
     end if;
end if;
end process;
y<=x and f;
end behav;

6 个解决方案

#1

每一个error都会指出错误出现的大致范围和修改方法，例如：Error (10500): VHDL syntax error at Vhdl2.vhd(17) near text ""; expecting "then"，是说你程序的第17行存在语法错误，在“”附近，本应该出现的是一个“then”，不一定对，这是软件自身做出的判断和修改，你可以作为参考

#2

未发现问题未发现问题

#3

写verilog的飘过，不明白为啥 start=0分支，对f没有赋值

#4

你写的VHDL有语法错误

#5

if clk'event and clk=’1’then中clk='1'单引号错了，你用的是’’，要输入法改成英文后的''；

#6

该回复于2018-01-16 15:59:05被管理员删除

#1

#2