Synergy CORTEX M 启动流程

时间:2023-03-08 17:40:11
Synergy CORTEX M 启动流程

1、启动文件“startup_S7G2.c”

  中断向量表地址指针:“0xe000ed08”

/* Vector table. */
BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_VECTOR) =
{
(exc_ptr_t)(&g_main_stack[] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
, /* Reserved */
, /* Reserved */
, /* Reserved */
, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
};

2、“入口函数”在“链接脚本”中配置,S7G2.ld

/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x0040000 /* 256K */
RAM (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 0x00A0000 /* 640K */
DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x0010000 /* 64K */
QSPI_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x0800000 /* 8M, Change in QSPI section below also */
SDRAM (rwx) : ORIGIN = 0x90000000, LENGTH = 0x2000000 /* 32M */
} ENTRY(Reset_Handler)

入口函数如下:

/***********************************************************************************************************************
* Function Name: Reset_Handler
* Description : MCU starts executing here out of reset. Main stack pointer is setup already.
* Arguments : none
* Return Value : none
***********************************************************************************************************************/
void Reset_Handler (void)
{
/* Initialize system using BSP. */
SystemInit(); /* Call user application. */
main(); while ()
{
/* Infinite Loop. */
}
}

HOOK设置 R_BSP_WarmStart(),用户可以有机会在“main()”执行前加入自己的操作。如:BOOT下判断是否有OTA升级。

void SystemInit (void)
{
#if ( defined ( __GNUC__ ) && defined (__VFP_FP__) && !defined (__SOFTFP__) ) || \
( defined ( __ICCARM__ ) && defined ( __ARMVFP__ ) && (__FPU_PRESENT == ) ) /* Enable the Cortex-M4 FPU only when -mfloat-abi=hard.
Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ /* Set bits 20-23 to enable CP10 and CP11 coprocessor */ /*LDRA_NOANALYSIS LDRA_INSPECTED below not working. */
/*LDRA_INSPECTED 96 S *//*LDRA_INSPECTED 93 S SCB is a CMSIS defined element over which we have no control.*/
SCB->CPACR = (uint32_t)((uint32_t)SCB->CPACR | (uint32_t)CP_MASK);
/*LDRA_ANALYSIS */
#endif /* Call Pre C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_PRE_C); /* Initialize grouped interrupts. */
bsp_group_interrupt_open(); /* Initialize FMI. */
g_fmi_on_fmi.init(); /* Initialize register protection. */
bsp_register_protect_open(); /* Configure system clocks using CGC module. */
bsp_clock_init(); /* Temporary fix to initialize ioport reference counter to 0, needed before C runtime init. This will be removed
* in the next release in favor of a more complete solution. */
HW_IOPORT_Init_Reference_Counter(); /* Initialize pins. */
g_ioport_on_ioport.init(&g_bsp_pin_cfg); /* Initialize C runtime environment. */
/* Zero out BSS */
#if defined(__GNUC__)
bsp_section_zero((uint8_t *)&__bss_start__, ((uint32_t)&__bss_end__ - (uint32_t)&__bss_start__));
#elif defined(__ICCARM__)
bsp_section_zero((uint8_t *)__section_begin(".bss"), (uint32_t)__section_size(".bss"));
#endif /* Copy initialized RAM data from ROM to RAM. */
#if defined(__GNUC__)
bsp_section_copy((uint8_t *)&__etext,
(uint8_t *)&__data_start__,
((uint32_t)&__data_end__ - (uint32_t)&__data_start__));
#elif defined(__ICCARM__)
bsp_section_copy((uint8_t *)__section_begin(".data_init"),
(uint8_t *)__section_begin(".data"),
(uint32_t)__section_size(".data"));
/* Copy functions to be executed from RAM. */
#pragma section=".code_in_ram"
#pragma section=".code_in_ram_init"
bsp_section_copy((uint8_t *)__section_begin(".code_in_ram_init"),
(uint8_t *)__section_begin(".code_in_ram"),
(uint32_t)__section_size(".code_in_ram"));
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
bsp_section_copy((uint8_t *)__section_begin("__DLIB_PERTHREAD_init"),
(uint8_t *)__section_begin("__DLIB_PERTHREAD"),
(uint32_t)__section_size("__DLIB_PERTHREAD_init"));
#endif /* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate(); /* Call Post C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_C); /* Initialize Static Constructors */
#if defined(__GNUC__)
/*LDRA_INSPECTED 219 S In the GCC compiler, __init_array_start and __init_array_end starts with underscore. */
/*LDRA_INSPECTED 219 S */
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = ; i < count; i++)
{
__init_array_start [i]();
}
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
__call_ctors(pibase, ilimit);
#endif /* Initialize the Hardware locks to 'Unlocked' */
bsp_init_hardware_locks(); /* Initialize ELC events that will be used to trigger NVIC interrupts. */
bsp_irq_cfg(); /* Initialize ELC. */
g_elc_on_elc.init(&g_elc_cfg); /* Call any BSP specific code. No arguments are needed so NULL is sent. */
bsp_init(NULL);
}

R_BSP_WarmStart()下实现的“BCH”升级

void R_BSP_WarmStart (bsp_warm_start_event_t event)
{
if (BSP_WARM_START_PRE_C == event)
{
/* C runtime environment has not been setup so you cannot use globals. System clocks and pins are not setup. */
} else if (BSP_WARM_START_POST_C == event)
{
/* if S5 is pressed */
if ( == ((R_IOPORT0->PCNTR2 >> ) & 0x1))
{
boot_status = ;
} /* if S4 is pressed */
else if ( == ((R_IOPORT0->PCNTR2 >> ) & 0x1))
{
boot_status = ;
} /* if S4 and S5 are not pressed */
else
{
/* Initialize the Hardware locks to 'Unlocked' */
bsp_init_hardware_locks(); ssp_err_t status; status = g_sf_bootloader_mcu.p_api->open(g_sf_bootloader_mcu.p_ctrl, g_sf_bootloader_mcu.p_cfg);
if (!status)
{
status = g_sf_bootloader_mcu.p_api->appStart(g_sf_bootloader_mcu.p_ctrl);
if (status)
{
/* Notify the bootloader that appStart failed */
boot_status = ; g_sf_bootloader_mcu.p_api->close(g_sf_bootloader_mcu.p_ctrl);
}
} else
{
/* Notify the bootloader that open failed */
boot_status = ;
}
}
} else
{
/* Do nothing */
}
}

当然也可以判断DATA FLASH数据作为是否升级的依据:

Synergy CORTEX M 启动流程